： We introduced a TaN/TiAl/top-TiN triple-layer to modulate the effective work function of a TiN-based metal gate stack by varying the TaN thickness and top-TiN technology process. The results show that a thinner TaN...： We introduced a TaN/TiAl/top-TiN triple-layer to modulate the effective work function of a TiN-based metal gate stack by varying the TaN thickness and top-TiN technology process. The results show that a thinner TaN and PVD-process top-TiN capping provide smaller effective work function （EWF）, and a thicker TaN and ALD-process top-TiN capping provides a larger EWF; here, the EWF shifts are from 4.25 to 4.56 eV. A physical understanding of the dependence of the EWF on the top-TiN technology process and TaN thickness is proposed. Compared with PVD-TiN room temperature process, the ALD-TiN 400 ℃ process provides more thermal budget. It would also promote more Al atoms to diffuse into the top-TiN rather than the bottom-TiN. Meanwhile, the thicker TaN prevents the Al atoms diffusing into the bottom-TiN. These facts induce the EWF to increase.展开更多
The resistivity, crystalline structure and effective work function （EWF） of reactive sputtered TaN has been investigated. As-deposited TaN films have an fcc structure. After post-metal annealing （PMA） at 900℃, th...The resistivity, crystalline structure and effective work function （EWF） of reactive sputtered TaN has been investigated. As-deposited TaN films have an fcc structure. After post-metal annealing （PMA） at 900℃, the TaN films deposited with a N2 flow rate greater than 6.5 sccm keep their fcc structure, while the films deposited with a N2 flow rate lower than 6.25 sccm exhibit a microstructure change. The flatband voltages of gate stacks with TaN films as gate electrodes on SiO2 and HfO2 are also measured. It is concluded that a dipole is formed at the dielectric-TaN interface and its contribution to the EWF of TaN changes with the Ta/N ratio in TaN, the underneath dielectric layer and the PMA conditions.展开更多
We evaluated the TiN/TaN/TiA1 triple-layer to modulate the effective work function （EWF） of a metal gate stack for the n-type metal-oxide-semiconductor （NMOS） devices application by varying the TiN/TaN thickness. ...We evaluated the TiN/TaN/TiA1 triple-layer to modulate the effective work function （EWF） of a metal gate stack for the n-type metal-oxide-semiconductor （NMOS） devices application by varying the TiN/TaN thickness. In this paper, the effective work function of EWF ranges from 4.22 to 4.56 eV with different thicknesses of TiN and TaN. The thinner TiN and/or thinner in situ TaN capping, the closer to conduction band of silicon the EWF is, which is appropriate for 2-D planar NMOS. Mid-gap work function behavior is observed with thicker TiN, thicker in situ TaN capping, indicating a strong potential candidate of metal gate material for replacement gate processed three-dimensional devices such as FIN shaped field effect transistors. The physical understandings of the sensitivity of EWF to TiN and TaN thickness are proposed. The thicker TiN prevents the A1 diffusion then induces the EWF to shift to mid-gap. However, the TaN plays a different role in effective work function tuning from TiN, due to the Ta-O dipoles formed at the interface between the metal gate and the high-k layer.展开更多
The dependences of Fermi-level pinning on interface state densities for the metal-dielectric, ploycrystalline silicon-dielectric, and metal silicide-dielectric interfaces are investigated by calculating their effectiv...The dependences of Fermi-level pinning on interface state densities for the metal-dielectric, ploycrystalline silicon-dielectric, and metal silicide-dielectric interfaces are investigated by calculating their effective work functions and their pinning factors. The Fermi-level pinning factors and effective work functions of the metal-dielectric interface are observed to be more susceptible to the increasing interface state densities, differing significantly from that of the ploycrystalline silicon-dielectric interface and the metal silicide-dielectric interface. The calculation results indicate that metal silicide gates with high-temperature resistance and low resistivity are a more promising choice for the design of gate materials in metal-oxide semiconductor（MOS） technology.展开更多
Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate （HK/MG） process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin F...Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate （HK/MG） process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer （PTSL） and source drain extension （SDE） doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function （EWF） MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the device＇s scaling.展开更多
We present an approach of GaAs MESFET incorporating the gate engineering effect to improve immunity against the short channel effects in order to enhance the scaling capability and the device performance for microwave...We present an approach of GaAs MESFET incorporating the gate engineering effect to improve immunity against the short channel effects in order to enhance the scaling capability and the device performance for microwave frequency applications. In this context, a physics-based model for I–V characteristics and various microwave characteristics such as transconductance, cut-off frequency and maximum frequency of oscillation of submicron triple material gate（TM） GaAs MESFET are developed. The reduced short channel effects have also been discussed in combined designs i.e. TM, DM and SM in order to show the impact of our approach on the GaAs MESFETs-based device design. The proposed analytical models have been verified by their good agreement with 2D numerical simulations. The models developed in this paper will be useful for submicron and microwave analysis for circuit design.展开更多
基金Project supported by the Important National Science&Technology Specific Projects(No.2009ZX02035)the National Natural Science Foundation of China(Nos.61176091,61306129)
文摘： We introduced a TaN/TiAl/top-TiN triple-layer to modulate the effective work function of a TiN-based metal gate stack by varying the TaN thickness and top-TiN technology process. The results show that a thinner TaN and PVD-process top-TiN capping provide smaller effective work function （EWF）, and a thicker TaN and ALD-process top-TiN capping provides a larger EWF; here, the EWF shifts are from 4.25 to 4.56 eV. A physical understanding of the dependence of the EWF on the top-TiN technology process and TaN thickness is proposed. Compared with PVD-TiN room temperature process, the ALD-TiN 400 ℃ process provides more thermal budget. It would also promote more Al atoms to diffuse into the top-TiN rather than the bottom-TiN. Meanwhile, the thicker TaN prevents the Al atoms diffusing into the bottom-TiN. These facts induce the EWF to increase.
基金Project supported by the State Key Development Program for Basic Research of China(No.2010CB934204)the National Natural Science Foundation of China(No.60825403)the National Key Projects of China(Nos.2009ZX-02302-004,2009ZX02023-005).
文摘The resistivity, crystalline structure and effective work function （EWF） of reactive sputtered TaN has been investigated. As-deposited TaN films have an fcc structure. After post-metal annealing （PMA） at 900℃, the TaN films deposited with a N2 flow rate greater than 6.5 sccm keep their fcc structure, while the films deposited with a N2 flow rate lower than 6.25 sccm exhibit a microstructure change. The flatband voltages of gate stacks with TaN films as gate electrodes on SiO2 and HfO2 are also measured. It is concluded that a dipole is formed at the dielectric-TaN interface and its contribution to the EWF of TaN changes with the Ta/N ratio in TaN, the underneath dielectric layer and the PMA conditions.
基金Project supported by the Important National Science & Technology Specific Projects(No.2009ZX02035)the National Natural Science Foundation of China(Nos.61176091,61306129)
文摘We evaluated the TiN/TaN/TiA1 triple-layer to modulate the effective work function （EWF） of a metal gate stack for the n-type metal-oxide-semiconductor （NMOS） devices application by varying the TiN/TaN thickness. In this paper, the effective work function of EWF ranges from 4.22 to 4.56 eV with different thicknesses of TiN and TaN. The thinner TiN and/or thinner in situ TaN capping, the closer to conduction band of silicon the EWF is, which is appropriate for 2-D planar NMOS. Mid-gap work function behavior is observed with thicker TiN, thicker in situ TaN capping, indicating a strong potential candidate of metal gate material for replacement gate processed three-dimensional devices such as FIN shaped field effect transistors. The physical understandings of the sensitivity of EWF to TiN and TaN thickness are proposed. The thicker TiN prevents the A1 diffusion then induces the EWF to shift to mid-gap. However, the TaN plays a different role in effective work function tuning from TiN, due to the Ta-O dipoles formed at the interface between the metal gate and the high-k layer.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61376096,61327813,and 11234007)
文摘The dependences of Fermi-level pinning on interface state densities for the metal-dielectric, ploycrystalline silicon-dielectric, and metal silicide-dielectric interfaces are investigated by calculating their effective work functions and their pinning factors. The Fermi-level pinning factors and effective work functions of the metal-dielectric interface are observed to be more susceptible to the increasing interface state densities, differing significantly from that of the ploycrystalline silicon-dielectric interface and the metal silicide-dielectric interface. The calculation results indicate that metal silicide gates with high-temperature resistance and low resistivity are a more promising choice for the design of gate materials in metal-oxide semiconductor（MOS） technology.
基金supported by the National 02 IC Projectsthe Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences
文摘Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate （HK/MG） process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer （PTSL） and source drain extension （SDE） doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function （EWF） MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the device＇s scaling.
文摘We present an approach of GaAs MESFET incorporating the gate engineering effect to improve immunity against the short channel effects in order to enhance the scaling capability and the device performance for microwave frequency applications. In this context, a physics-based model for I–V characteristics and various microwave characteristics such as transconductance, cut-off frequency and maximum frequency of oscillation of submicron triple material gate（TM） GaAs MESFET are developed. The reduced short channel effects have also been discussed in combined designs i.e. TM, DM and SM in order to show the impact of our approach on the GaAs MESFETs-based device design. The proposed analytical models have been verified by their good agreement with 2D numerical simulations. The models developed in this paper will be useful for submicron and microwave analysis for circuit design.
