Based on the minimum settling time （MST） theory and step-response analysis of the second order system in active switched capacitor （SC） networks, a novel clock feedthrough frequency compensation （CFFC） method fo...Based on the minimum settling time （MST） theory and step-response analysis of the second order system in active switched capacitor （SC） networks, a novel clock feedthrough frequency compensation （CFFC） method for a folded-cascode OTA is proposed. The damping factor r/is adjusted by using MOS capacitors to introduce clock feedthrough so that the OTA can obtain the MST state and thus achieve fast settling. Research results indicate that the settling time of the compensated OTA is reduced by 22.7% ;as the capacitor load varies from 0.5 to 2.5pF,the improved settling time increases approximately linearly from 3.62 to 4.46ns： for VGA application, fast settling can also be achieved by modifying the MOS capacitor value accordingly when the closed loop gain of the compensated OTA varies.展开更多
A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard f...A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory （NVM） is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 #m technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 #s over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about -115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc. The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.展开更多
文摘Based on the minimum settling time （MST） theory and step-response analysis of the second order system in active switched capacitor （SC） networks, a novel clock feedthrough frequency compensation （CFFC） method for a folded-cascode OTA is proposed. The damping factor r/is adjusted by using MOS capacitors to introduce clock feedthrough so that the OTA can obtain the MST state and thus achieve fast settling. Research results indicate that the settling time of the compensated OTA is reduced by 22.7% ;as the capacitor load varies from 0.5 to 2.5pF,the improved settling time increases approximately linearly from 3.62 to 4.46ns： for VGA application, fast settling can also be achieved by modifying the MOS capacitor value accordingly when the closed loop gain of the compensated OTA varies.
基金Project supported by the National Natural Science Foundation of China(No.60976023)the National Science and Technology Major Project of China(Nos.2009ZX03007-001,2012ZX03004007-002)
文摘A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory （NVM） is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 #m technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 #s over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about -115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc. The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.
