In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper ...In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.展开更多
The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arr...The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.展开更多
Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid developme...Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.展开更多
Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is co...Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is constructed.The dynamics characteristics including bifurcation behavior and coexistence of the system are analyzed in detail,the latter reveals abundant coexisting flows.Furthermore,the proposed system passes the NIST tests and has been implemented physically by FPGA.Compared to the multi-scroll dissipative chaos,the experimental portraits of the proposed system show better ergodicity,which have potential application value in secure communication and image encryption.展开更多
Afuzzy controller based oni mproved Generalized-Membership-Function(GMF) algorithmfor afuel cell generationsys-tem wasintroduced.Under the demands on control in application of the converter,a Field Programmable Gate A...Afuzzy controller based oni mproved Generalized-Membership-Function(GMF) algorithmfor afuel cell generationsys-tem wasintroduced.Under the demands on control in application of the converter,a Field Programmable Gate Array(FPGA) re-alization method to manage the power flow was given.This control systembased onthe proposed modified GMF was proved to bea universal approxi mation systemin theory.The fuzzy control technique was combined with Eletronic Design Automatic(EDA)technique and a paralleling fuzzy controller was i mplemented in FPGA.Paralleling fuzzy controller based oni mproved GMF algo-rithm wasi mplemented on a Cyclone FPGA.The result of si mulation based on QuartusII confirmed the validity of the proposed method.展开更多
To improve the path slack of Field Programmable Gate Array(FPGA), this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of ...To improve the path slack of Field Programmable Gate Array(FPGA), this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is analyzed, and by constructing a collocation table of delay model that takes into account the multi-corner process, the complex statistical static timing analysis is successfully translated into a simple classical static timing analysis. Then, based on the hybrid routing strategy of rip-up-retry and pathfinder, by adjusting the critical path which detours a long distance, the critical path delay is reduced and the path slack is optimized. Experimental results show that, using the hybrid routing strategy, the number of paths with negative slack can be optimized(reduced) by 85.8% on average compared with the Versatile Place and Route(VPR) timing-driven routing algorithm, while the run-time is only increased by 15.02% on average.展开更多
This paper introduces a switched hyperchaotic system that changes its behavior randomly from one subsystem to another via two switch functions, and its characteristics of symmetry, dissipation, equilibrium, bifurcatio...This paper introduces a switched hyperchaotic system that changes its behavior randomly from one subsystem to another via two switch functions, and its characteristics of symmetry, dissipation, equilibrium, bifurcation diagram, basic dynamics have been analyzed. The hardware implementation of the system is based on Field Programmable Gate Array (FPGA). It is shown that the experimental results are identical with numerical simulations, and the chaotic trajectories are much more complex.展开更多
An internal single event upset(SEU)mitigation technique is proposed,which reads back the configuration frames from the static random access memory(SRAM)-based field programmable gate array(FPGA)through an internal por...An internal single event upset(SEU)mitigation technique is proposed,which reads back the configuration frames from the static random access memory(SRAM)-based field programmable gate array(FPGA)through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy(TMR),which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.展开更多
High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the impleme...High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.展开更多
A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to ...A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to reduce power consumption and silicon area. The compression algorithm includes color space transform,uniform quantization, sub-sampling, differential pulse code modulation(DPCM) and Golomb-Rice code. The algorithm is tested in a field programmable gate array(FPGA) development board, and the final result achieves 80% compression rate at 40 dB peak signal to noise ratio(PSNR). The algorithm has high image compression efficiency and low power consumption, compared to other existing works. The system is composed of the following three parts: image capsule endoscope, portable wireless receiver and host computer software. The software and hardware design of the three parts are disscussed in details.展开更多
We present a novel method to implement the radix-2 fast Fourier transform (FFT) algorithm on field programmable gate arrays (FPGA).The FFT architecture exploits parallelism by having more pipelined units in the stages...We present a novel method to implement the radix-2 fast Fourier transform (FFT) algorithm on field programmable gate arrays (FPGA).The FFT architecture exploits parallelism by having more pipelined units in the stages,and more parallel units within a stage.It has the noticeable advantages of high speed and more efficient resource utilization by employing four ganged butterfly engines (GBEs),and can be well matched to the placement of the resources on the FPGA.We adopt the decimation-infrequency (DIF) radix-2 FFT algorithm and implement the FFT processor on a state-of-the-art FPGA.Experimental results show that the processor can compute 1024-point complex radix-2 FFT in about 11 μs with a clock frequency of 200 MHz.展开更多
In this paper,a fast-speed and real-time online rail inspection method based on half-cycle orthogonal power demodulation algorithm is proposed.For this method,the power characters of de-tection signal which represent ...In this paper,a fast-speed and real-time online rail inspection method based on half-cycle orthogonal power demodulation algorithm is proposed.For this method,the power characters of de-tection signal which represent the degree of rail track can be calculated using only half-cycle detec-tion signal because of the symmetry characteristic of detected sine signal and reference signal.The theoretical analysis,simulation results and experiment results show that the demodulation preci-sion of proposed method is almost equal to fast Fourier transform(FFT)demodulation method and orthogonal demodulation method,but has high demodulation efficiency and less FPGA resources cost.A high-speed experiment system based on three coils structured sensor is built for rail inspec-tion experiment at a moving speed of 200 km/h.The experiment results show that proposed meth-od is more effective for rail inspection and the time resolution of proposed method is double of clas-sic method that based on FFT and orthogonal.展开更多
Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-F...Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.展开更多
An efficient high precision biorthogonal 9/7 wavelet filter structure for image processing applications was proposed. This structure aimed at high precision applications. A precision improved distributed algorithms (D...An efficient high precision biorthogonal 9/7 wavelet filter structure for image processing applications was proposed. This structure aimed at high precision applications. A precision improved distributed algorithms (DA) had been proposed. Comparing with traditional DA implementations, the new DA had higher precision while preserves smaller area. The proposed structure was verified in Spartan-6 field programmable gate array (FPGA) and achieved 200 MHz operation frequency. The peak signal to noise ratio (PSNR) of reconstructed image (Lena) achieves 74 dB which is very high comparing with other implementations.展开更多
If single chip micro computer controls light-emitting diode(LED),it needs abundant peripheral resources,but in this way,it is not convenient to be expanded,modified and maintained.In order to overcome these shortcomin...If single chip micro computer controls light-emitting diode(LED),it needs abundant peripheral resources,but in this way,it is not convenient to be expanded,modified and maintained.In order to overcome these shortcomings,field programmable gate array(FPGA)is used to control LED.The hardware design uses low power consumption and high performance device EP1C6Q240C8.Quartus II is the software development environment.There are three modules built under the software development environment:divided clock module,word stock module and LED dot matrix display module,and these independent modules are connected to be a whole system.Finally,32×64 dot matrix display is realized successfully.It is convenient for the customer to adjust the three independent modules according to actual demands and it is easier to realize online updation.展开更多
This paper will provide some insights on the application of Field Programmable Gate Array (FPGA) in process tomography. The focus of this paper will be to investigate the performance of the technology with respect to ...This paper will provide some insights on the application of Field Programmable Gate Array (FPGA) in process tomography. The focus of this paper will be to investigate the performance of the technology with respect to various tomography systems and comparison to other similar technologies including the Application Specific Integrated Circuit (ASIC), Graphics Processing Unit (GPU) and the microcontroller. Fundamentally, the FPGA is primarily used in the Data Acquisition System (DAQ) due to its better performance and better trade-off as compared to competitor technologies. However, the drawback of using FPGA is that it is relatively more expensive.展开更多
This paper presents the independent source tied photovoltaic (PV) based three-phase three-level diode-clamped-multilevel inverter (DCD-MLI) utilizing field programmable gate array (FPGA) controller. The maximum power ...This paper presents the independent source tied photovoltaic (PV) based three-phase three-level diode-clamped-multilevel inverter (DCD-MLI) utilizing field programmable gate array (FPGA) controller. The maximum power point (MPP) is tracked by using fuzzy logic algorithm. Employed for gating signal generation, the space vector modulation (SVM) strategy eradicates the complexity in determining the reference vector location, the ON-time calculations and switching state selection. A digital proportional integral (PI) control algorithm is implemented on a FPGA to keep the current injected into the independent source (grid) sinusoidal and to achieve high dynamic performance with low total harmonic distortion (THD) of output voltage and output current which are 0.97% and 1.26%. With the proposed configuration, the adjustments of modulation index and phase angle are synthesized onto a FPGA by means of hardware description language (VHDL). The efficacy of the scheme is verified through simulation study. To confirm the feasibility of the scheme, experimental studies are carried out on a scaled-down laboratory prototype.展开更多
A program of adaptive quadrature demodulation is proposed to supply the gaps in the traditional analog detection technology of a silicon micro-machined gyroscope (SMG). This program is suitable for digital phase locke...A program of adaptive quadrature demodulation is proposed to supply the gaps in the traditional analog detection technology of a silicon micro-machined gyroscope (SMG). This program is suitable for digital phase locked loop (DPLL) drive technology that proposed in other papers. In addition the program adopts an adaptive filtering algorithm, which selects the in-phase and quadrature components that are outputs of the DPLL of the SMG's drive mode as reference signals to update the amplitude of the in-phase and quadrature components of the input signal by iteratively. An objective of the program is to minimize the mean square error of the accurate amplitudes and the estimated amplitudes of SMG's detection mode. The simulation and test results prove the feasibility of the program that lays the foundation for the further improvement of the SMG's system performance and the implementation of the SMG system's self-calibration and self-demarcation in future.展开更多
An optimized commutation method based on backpropagation(BP)neural network is proposed to resolve the low stability and high-power consumption caused by inaccurate commutation point prediction in conventional commutat...An optimized commutation method based on backpropagation(BP)neural network is proposed to resolve the low stability and high-power consumption caused by inaccurate commutation point prediction in conventional commutation strategy during acceleration and deceleration.This article also builds a complete brushless DC motor drive system based on the GD32F103 micro control unit(MCU),with an Artix-7 XC7A35T field programmable gate array(FPGA)to meet the performance requirements of neural network calculation for real-time motor commutation control.Experimental results show that the proposed optimization strategy can effectively improve the system stability during system acceleration and deceleration,and reduce the current spikes generated during speed chan-ges.The system power consumption is reduced by about 11.7%on average.展开更多
Electron cyclotron resonance heating (ECRH) system is one of the most important Tokamak auxiliary heating methods. However, there are growing demands for ECRH system as the physical experiments progress which meanwhil...Electron cyclotron resonance heating (ECRH) system is one of the most important Tokamak auxiliary heating methods. However, there are growing demands for ECRH system as the physical experiments progress which meanwhile adds the difficulty of designing and building the control system of its power source. In this paper, the method of designing a control system based on Single Chip Microcomputer (SCM) and Field Programmable Gate Array (FPGA) is introduced according to its main requirements. The experimental results show that the control system in this paper achieves the conversion of different working modes, gets exact timing, and realizes the failure protection in 10us thus can be used in the ECRH system.展开更多
基金Science &Technology Plan Foundation of Hunan Province,China(No.2010F3102)Science Research Foundation of Hunan Province,China(No.08C392)
文摘In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.
基金Supported by the CAS/SAFEA International Partnership Program for Creative Research Teams,National High Technology Research and Develop Program of China(2012AA012301)National Science and Technology Major Project of China(2013ZX03006004)
文摘The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.
基金Supported by National Natural Science Foundation of China(No.61271149)National High Technology Research and Development Program of China(No.2012AA-012301)National Science and Technology Major Project of China(No.2013ZX03006004)
文摘Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.
基金Project supported by the Natural Science Foundation of Tianjin,China(Grant No.18JCYBJC87700)the Natural Science Foundation of China(Grant No.61603274)。
文摘Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is constructed.The dynamics characteristics including bifurcation behavior and coexistence of the system are analyzed in detail,the latter reveals abundant coexisting flows.Furthermore,the proposed system passes the NIST tests and has been implemented physically by FPGA.Compared to the multi-scroll dissipative chaos,the experimental portraits of the proposed system show better ergodicity,which have potential application value in secure communication and image encryption.
文摘Afuzzy controller based oni mproved Generalized-Membership-Function(GMF) algorithmfor afuel cell generationsys-tem wasintroduced.Under the demands on control in application of the converter,a Field Programmable Gate Array(FPGA) re-alization method to manage the power flow was given.This control systembased onthe proposed modified GMF was proved to bea universal approxi mation systemin theory.The fuzzy control technique was combined with Eletronic Design Automatic(EDA)technique and a paralleling fuzzy controller was i mplemented in FPGA.Paralleling fuzzy controller based oni mproved GMF algo-rithm wasi mplemented on a Cyclone FPGA.The result of si mulation based on QuartusII confirmed the validity of the proposed method.
基金Supported by National High Technology Research and Develop Program of China(No.2012AA012301)the CAS/SAFEA International Partnership Program for Creative Research Teams
文摘To improve the path slack of Field Programmable Gate Array(FPGA), this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is analyzed, and by constructing a collocation table of delay model that takes into account the multi-corner process, the complex statistical static timing analysis is successfully translated into a simple classical static timing analysis. Then, based on the hybrid routing strategy of rip-up-retry and pathfinder, by adjusting the critical path which detours a long distance, the critical path delay is reduced and the path slack is optimized. Experimental results show that, using the hybrid routing strategy, the number of paths with negative slack can be optimized(reduced) by 85.8% on average compared with the Versatile Place and Route(VPR) timing-driven routing algorithm, while the run-time is only increased by 15.02% on average.
文摘This paper introduces a switched hyperchaotic system that changes its behavior randomly from one subsystem to another via two switch functions, and its characteristics of symmetry, dissipation, equilibrium, bifurcation diagram, basic dynamics have been analyzed. The hardware implementation of the system is based on Field Programmable Gate Array (FPGA). It is shown that the experimental results are identical with numerical simulations, and the chaotic trajectories are much more complex.
基金Supported by the National High Technology and Development Program of China(2013AA1548)
文摘An internal single event upset(SEU)mitigation technique is proposed,which reads back the configuration frames from the static random access memory(SRAM)-based field programmable gate array(FPGA)through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy(TMR),which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.
基金the National Science Foundation of China(Nos.60934007 and 61074060)the Postdoctoral Science Foundation of China(No.20090460627)+2 种基金the Postdoctoral Scientific Program of Shanghai (No.10R21414600)the Specialized Research Fund for the Doctoral Program of Higher Education (No.20070248004)the China Postdoctoral Science Foundation Special Support(No.201003272)
文摘High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.
基金the National Nature Science Foundation of China(Nos.30800235,31271069)
文摘A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to reduce power consumption and silicon area. The compression algorithm includes color space transform,uniform quantization, sub-sampling, differential pulse code modulation(DPCM) and Golomb-Rice code. The algorithm is tested in a field programmable gate array(FPGA) development board, and the final result achieves 80% compression rate at 40 dB peak signal to noise ratio(PSNR). The algorithm has high image compression efficiency and low power consumption, compared to other existing works. The system is composed of the following three parts: image capsule endoscope, portable wireless receiver and host computer software. The software and hardware design of the three parts are disscussed in details.
文摘We present a novel method to implement the radix-2 fast Fourier transform (FFT) algorithm on field programmable gate arrays (FPGA).The FFT architecture exploits parallelism by having more pipelined units in the stages,and more parallel units within a stage.It has the noticeable advantages of high speed and more efficient resource utilization by employing four ganged butterfly engines (GBEs),and can be well matched to the placement of the resources on the FPGA.We adopt the decimation-infrequency (DIF) radix-2 FFT algorithm and implement the FFT processor on a state-of-the-art FPGA.Experimental results show that the processor can compute 1024-point complex radix-2 FFT in about 11 μs with a clock frequency of 200 MHz.
基金supported by the National Natural Science Found-ation of China(No.61771041).
文摘In this paper,a fast-speed and real-time online rail inspection method based on half-cycle orthogonal power demodulation algorithm is proposed.For this method,the power characters of de-tection signal which represent the degree of rail track can be calculated using only half-cycle detec-tion signal because of the symmetry characteristic of detected sine signal and reference signal.The theoretical analysis,simulation results and experiment results show that the demodulation preci-sion of proposed method is almost equal to fast Fourier transform(FFT)demodulation method and orthogonal demodulation method,but has high demodulation efficiency and less FPGA resources cost.A high-speed experiment system based on three coils structured sensor is built for rail inspec-tion experiment at a moving speed of 200 km/h.The experiment results show that proposed meth-od is more effective for rail inspection and the time resolution of proposed method is double of clas-sic method that based on FFT and orthogonal.
基金Supported by the National Natural Science Foundation of China(No.61106033)
文摘Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.
文摘An efficient high precision biorthogonal 9/7 wavelet filter structure for image processing applications was proposed. This structure aimed at high precision applications. A precision improved distributed algorithms (DA) had been proposed. Comparing with traditional DA implementations, the new DA had higher precision while preserves smaller area. The proposed structure was verified in Spartan-6 field programmable gate array (FPGA) and achieved 200 MHz operation frequency. The peak signal to noise ratio (PSNR) of reconstructed image (Lena) achieves 74 dB which is very high comparing with other implementations.
文摘If single chip micro computer controls light-emitting diode(LED),it needs abundant peripheral resources,but in this way,it is not convenient to be expanded,modified and maintained.In order to overcome these shortcomings,field programmable gate array(FPGA)is used to control LED.The hardware design uses low power consumption and high performance device EP1C6Q240C8.Quartus II is the software development environment.There are three modules built under the software development environment:divided clock module,word stock module and LED dot matrix display module,and these independent modules are connected to be a whole system.Finally,32×64 dot matrix display is realized successfully.It is convenient for the customer to adjust the three independent modules according to actual demands and it is easier to realize online updation.
文摘This paper will provide some insights on the application of Field Programmable Gate Array (FPGA) in process tomography. The focus of this paper will be to investigate the performance of the technology with respect to various tomography systems and comparison to other similar technologies including the Application Specific Integrated Circuit (ASIC), Graphics Processing Unit (GPU) and the microcontroller. Fundamentally, the FPGA is primarily used in the Data Acquisition System (DAQ) due to its better performance and better trade-off as compared to competitor technologies. However, the drawback of using FPGA is that it is relatively more expensive.
文摘This paper presents the independent source tied photovoltaic (PV) based three-phase three-level diode-clamped-multilevel inverter (DCD-MLI) utilizing field programmable gate array (FPGA) controller. The maximum power point (MPP) is tracked by using fuzzy logic algorithm. Employed for gating signal generation, the space vector modulation (SVM) strategy eradicates the complexity in determining the reference vector location, the ON-time calculations and switching state selection. A digital proportional integral (PI) control algorithm is implemented on a FPGA to keep the current injected into the independent source (grid) sinusoidal and to achieve high dynamic performance with low total harmonic distortion (THD) of output voltage and output current which are 0.97% and 1.26%. With the proposed configuration, the adjustments of modulation index and phase angle are synthesized onto a FPGA by means of hardware description language (VHDL). The efficacy of the scheme is verified through simulation study. To confirm the feasibility of the scheme, experimental studies are carried out on a scaled-down laboratory prototype.
文摘A program of adaptive quadrature demodulation is proposed to supply the gaps in the traditional analog detection technology of a silicon micro-machined gyroscope (SMG). This program is suitable for digital phase locked loop (DPLL) drive technology that proposed in other papers. In addition the program adopts an adaptive filtering algorithm, which selects the in-phase and quadrature components that are outputs of the DPLL of the SMG's drive mode as reference signals to update the amplitude of the in-phase and quadrature components of the input signal by iteratively. An objective of the program is to minimize the mean square error of the accurate amplitudes and the estimated amplitudes of SMG's detection mode. The simulation and test results prove the feasibility of the program that lays the foundation for the further improvement of the SMG's system performance and the implementation of the SMG system's self-calibration and self-demarcation in future.
基金the National Key Research and Development Program(No.2017YFB0406204,2016YFC0105604)Beijing Science and Technology Projects(No.Z181100003818002)Science and Technology Service Network Initiative(No.FJ-STS-QYZX-099,KFJ-STS-ZDTP-069).
文摘An optimized commutation method based on backpropagation(BP)neural network is proposed to resolve the low stability and high-power consumption caused by inaccurate commutation point prediction in conventional commutation strategy during acceleration and deceleration.This article also builds a complete brushless DC motor drive system based on the GD32F103 micro control unit(MCU),with an Artix-7 XC7A35T field programmable gate array(FPGA)to meet the performance requirements of neural network calculation for real-time motor commutation control.Experimental results show that the proposed optimization strategy can effectively improve the system stability during system acceleration and deceleration,and reduce the current spikes generated during speed chan-ges.The system power consumption is reduced by about 11.7%on average.
文摘Electron cyclotron resonance heating (ECRH) system is one of the most important Tokamak auxiliary heating methods. However, there are growing demands for ECRH system as the physical experiments progress which meanwhile adds the difficulty of designing and building the control system of its power source. In this paper, the method of designing a control system based on Single Chip Microcomputer (SCM) and Field Programmable Gate Array (FPGA) is introduced according to its main requirements. The experimental results show that the control system in this paper achieves the conversion of different working modes, gets exact timing, and realizes the failure protection in 10us thus can be used in the ECRH system.
