The improvement of the characteristics of grooved-gate MOSFETs compared to the planar devices is attributed to the corner effect of the surface potential along the channel. In this paper we propose an analytical model...The improvement of the characteristics of grooved-gate MOSFETs compared to the planar devices is attributed to the corner effect of the surface potential along the channel. In this paper we propose an analytical model of the surface potential distribution based on the solution of two-dimensional Poisson equation in cylindrical coordinates utilizing the cylinder approximation and the structure parameters such as the concave corner θ0. The relationship between the minimum surface potential and the structure parameters is theoretically analysed. Results confirm that the bigger the concave corner, the more obvious the corner effect. The corner effect increases the threshold voltage of the grooved-gate MOSFETs, so the better is the short channel effect （SCE） immunity.展开更多
We investigate the negative bias temperature instability （NBTI） of 90nm pMOSFETs under various temperatures and stress gate voltages （Vg）. We also study models of the time （t） ,temperature （T） ,and stress Vg d...We investigate the negative bias temperature instability （NBTI） of 90nm pMOSFETs under various temperatures and stress gate voltages （Vg）. We also study models of the time （t） ,temperature （T） ,and stress Vg dependence of 90nm pMOSFETs NBTI degradation. The time model and temperature model are similar to previ- ous studies, with small difference in the key coefficients. A power-law model is found to hold for Vg, which is different from the conventional exponential Vg model. The new model is more predictive than the exponential model when taking lower stress Vg into account.展开更多
在通常适合于制作埋沟 Si Ge NMOSFET的 Si/弛豫 Si Ge/应变 Si/弛豫 Si Ge缓冲层 /渐变 Ge组分层的结构上 ,制作成功了 Si Ge PMOSFET.这种 Si Ge PMOSFET将更容易与 Si Ge NMOSFET集成 ,用于实现 Si Ge CMOS.实验测得这种结构的 Si Ge...在通常适合于制作埋沟 Si Ge NMOSFET的 Si/弛豫 Si Ge/应变 Si/弛豫 Si Ge缓冲层 /渐变 Ge组分层的结构上 ,制作成功了 Si Ge PMOSFET.这种 Si Ge PMOSFET将更容易与 Si Ge NMOSFET集成 ,用于实现 Si Ge CMOS.实验测得这种结构的 Si Ge PMOSFET在栅压为 3.5 V时最大饱和跨导比用作对照的 Si PMOS提高约 2倍 ,而与常规的应变 Si展开更多
Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular be...Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.展开更多
为研究深亚微米尺度下应变 Si Ge沟改进 PMOSFET器件性能的有效性 ,运用二维数值模拟程序MEDICI模拟和分析了 0 .1 8μm有效沟长 Si Ge PMOS及 Si PMOS器件特性。Si Ge PMOS垂直方向采用 Si/Si Ge/Si结构 ,横向结构同常规 PMOS,N+ -pol...为研究深亚微米尺度下应变 Si Ge沟改进 PMOSFET器件性能的有效性 ,运用二维数值模拟程序MEDICI模拟和分析了 0 .1 8μm有效沟长 Si Ge PMOS及 Si PMOS器件特性。Si Ge PMOS垂直方向采用 Si/Si Ge/Si结构 ,横向结构同常规 PMOS,N+ -poly栅结合 P型δ掺杂层获得了合理阈值电压及空穴局域化。研究表明 ,经适当设计的 Si Ge PMOS比对应 Si PMOS的 IDmax、gm、f T均提高 1 0 0 %以上 ,表明深亚微米尺度 Si展开更多
基金Project supported by the National Natural Science Foundation of China （Grant No 603776024）.
文摘The improvement of the characteristics of grooved-gate MOSFETs compared to the planar devices is attributed to the corner effect of the surface potential along the channel. In this paper we propose an analytical model of the surface potential distribution based on the solution of two-dimensional Poisson equation in cylindrical coordinates utilizing the cylinder approximation and the structure parameters such as the concave corner θ0. The relationship between the minimum surface potential and the structure parameters is theoretically analysed. Results confirm that the bigger the concave corner, the more obvious the corner effect. The corner effect increases the threshold voltage of the grooved-gate MOSFETs, so the better is the short channel effect （SCE） immunity.
文摘We investigate the negative bias temperature instability （NBTI） of 90nm pMOSFETs under various temperatures and stress gate voltages （Vg）. We also study models of the time （t） ,temperature （T） ,and stress Vg dependence of 90nm pMOSFETs NBTI degradation. The time model and temperature model are similar to previ- ous studies, with small difference in the key coefficients. A power-law model is found to hold for Vg, which is different from the conventional exponential Vg model. The new model is more predictive than the exponential model when taking lower stress Vg into account.
文摘研究了最大栅电流应力 (即 p MOSFET最坏退化情况 )下 p MOSFET栅电流的退化特性 .实验发现 ,在最大栅电流应力下 ,p MOSFET栅电流随应力时间会发生很大下降 ,而且在应力初期和应力末期栅电流的下降规律均会偏离公认的指数规律 .给出了所有这些现象的详细物理解释 ,并在此基础上提出了一种新的用于 p
文摘在通常适合于制作埋沟 Si Ge NMOSFET的 Si/弛豫 Si Ge/应变 Si/弛豫 Si Ge缓冲层 /渐变 Ge组分层的结构上 ,制作成功了 Si Ge PMOSFET.这种 Si Ge PMOSFET将更容易与 Si Ge NMOSFET集成 ,用于实现 Si Ge CMOS.实验测得这种结构的 Si Ge PMOSFET在栅压为 3.5 V时最大饱和跨导比用作对照的 Si PMOS提高约 2倍 ,而与常规的应变 Si
文摘Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.
文摘为研究深亚微米尺度下应变 Si Ge沟改进 PMOSFET器件性能的有效性 ,运用二维数值模拟程序MEDICI模拟和分析了 0 .1 8μm有效沟长 Si Ge PMOS及 Si PMOS器件特性。Si Ge PMOS垂直方向采用 Si/Si Ge/Si结构 ,横向结构同常规 PMOS,N+ -poly栅结合 P型δ掺杂层获得了合理阈值电压及空穴局域化。研究表明 ,经适当设计的 Si Ge PMOS比对应 Si PMOS的 IDmax、gm、f T均提高 1 0 0 %以上 ,表明深亚微米尺度 Si
