Hot carrier induced (HCI) degradation of surface channel n MOSFETs with different oxide thicknesses is investigated under maximum substrate current condition.Results show that the key parameters m and n of H...Hot carrier induced (HCI) degradation of surface channel n MOSFETs with different oxide thicknesses is investigated under maximum substrate current condition.Results show that the key parameters m and n of Hu's lifetime prediction model have a close relationship with oxide thickness.Furthermore,a linear relationship is found between m and n .Based on this result,the lifetime prediction model can be expended to the device with thinner oxides.展开更多
Hot carrier effect（HCE） is studied on annular NMOS and two-edged NMOS such as H-shape gate NMOS, T-shape gate NMOS and common two-edged NMOS.Based on the chemical reaction equation of HCE degradation and a geometry ...Hot carrier effect（HCE） is studied on annular NMOS and two-edged NMOS such as H-shape gate NMOS, T-shape gate NMOS and common two-edged NMOS.Based on the chemical reaction equation of HCE degradation and a geometry dependent reaction diffusion equation,a HCE degradation model for annular NMOS and two-edged NMOS is proposed.According to this model,we conclude that the time exponent of the threshold voltage degradation depends on the configuration of the gate,and annular NMOS has more serious HCE degradation than two-edged NMOS.The design,fabrication and HCE experiments of these NMOS in a 0.5-μm PD SOI process verify the correctness of the conclusion.展开更多
Hot carrier effects of p MOSFETs with different oxide thicknesses are studied in low gate voltage range.All electrical parameters follow a power law relationship with stress time,but degradation slope is dependent ...Hot carrier effects of p MOSFETs with different oxide thicknesses are studied in low gate voltage range.All electrical parameters follow a power law relationship with stress time,but degradation slope is dependent on gate voltage.For the devices with thicker oxides,saturated drain current degradation has a close relationship with the product of gate current and electron fluence.For small dimensional devices,saturated drain current degradation has a close relationship with the electron fluence.This degradation model is valid for p MOSFETs with 0 25μm channel length and different gate oxide thicknesses.展开更多
The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is me...The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.展开更多
Annular gate nMOSFETs are frequently used in spaceborne integrated circuits due to their intrinsic good capability of resisting total ionizing dose （TID） effect. However, their capability of resisting the hot carrie...Annular gate nMOSFETs are frequently used in spaceborne integrated circuits due to their intrinsic good capability of resisting total ionizing dose （TID） effect. However, their capability of resisting the hot carrier effect （HCE） has also been proven to be very weak. In this paper, the reason why the annular gate nMOSFETs have good TID but bad HCE resistance is discussed in detail, and an improved design to locate the source contacts only along one side of the annular gate is used to weaken the HCE degradation. The good TID and HCE hardened capability of the design are verified by the experiments for I/O and core nMOSFETs in a 0.18 μm bulk CMOS technology. In addition, the shortcoming of this design is also discussed and the TID and the HCE characteristics of the replacers （the annular source nMOSFETs） are also studied to provide a possible alternative for the designers.展开更多
The hot carrier effect （HCE） of an ultra-deep sub-micron p-channel metal–oxide semiconductor field-effect transistor （pMOSFET） is investigated in this paper. Experiments indicate that the generation of positively...The hot carrier effect （HCE） of an ultra-deep sub-micron p-channel metal–oxide semiconductor field-effect transistor （pMOSFET） is investigated in this paper. Experiments indicate that the generation of positively charged interface states is the predominant mechanism in the case of the ultra-deep sub-micron pMOSFET. The relation of the pMOSFET hot carrier degradation to stress time （t）, channel width （W ）, channel length （L）, and stress voltage （Vd ） is then discussed. Based on the relation, a lifetime prediction model is proposed, which can predict the lifetime of the ultra-deep sub-micron pMOSFET accurately and reflect the influence of the factors on hot carrier degradation directly.展开更多
Grooved gate structure Metal-Oxide-Semiconductor (MOS) device is consideredas the most promising candidate used in deep and super-deep sub-micron region, for it cansuppress hot carrier effect and short channel effect ...Grooved gate structure Metal-Oxide-Semiconductor (MOS) device is consideredas the most promising candidate used in deep and super-deep sub-micron region, for it cansuppress hot carrier effect and short channel effect deeply. Based on the hydrodynamic energytransport model, using two-dimensional device simulator Medici, the relation between structureparameters and hot carrier effect immunity for deep-sub-micron N-channel MOSFET's is studiedand compared with that of counterpart conventional planar device in this paper. The examinedstructure parameters include negative junction depth, concave corner and effective channel length.Simulation results show that grooved gate device can suppress hot carrier effect deeply even indeep sub-micron region. The studies also indicate that hot carrier effect is strongly influencedby the concave corner and channel length for grooved gate device. With the increase of concavecorner, the hot carrier effect in grooved gate MOSFET decreases sharply, and with the reducingof effective channel length, the hot carrier effect becomes large.展开更多
A compact model for LDD MOSFET is proposed,which involves the hyperbolic tangent function description and the physics of device with emphasis on the substrate current modeling.The simulation results demonstrate good ...A compact model for LDD MOSFET is proposed,which involves the hyperbolic tangent function description and the physics of device with emphasis on the substrate current modeling.The simulation results demonstrate good agreement with measurement,and show that deep submicron LDD MOSFET has larger substrate current than submicron device does.The improved model costs low computation consumption,and is effective in manifestation of hot carrier effect and other effects in deep submicron devices,in turn is suitable for design and reliability analysis of scaling down devices.展开更多
Utilizing plasmonic effects to assist electrochemical reactions exhibits a huge potential in tuning the reaction activities and product selectivity,which is most appealing especially in chemical reactions with multipl...Utilizing plasmonic effects to assist electrochemical reactions exhibits a huge potential in tuning the reaction activities and product selectivity,which is most appealing especially in chemical reactions with multiple products,such as CO_(2)reduction reaction(CO_(2)RR).However,a comprehensive review of the development and the underlying mechanisms in plasmon-assisted electrocatalytic CO_(2)RR remains few and far between.Herein,the fundamentals of localized surface plasmonic resonance(LSPR)excitation and the properties of typical plasmonic metals(including Au,Ag,and Cu)are retrospected.Subsequently,the potential mechanisms of plasmonic effects(such as hot carrier effects and photothermal effects)on the reaction performance in the field of plasmon-assisted electrocatalytic CO_(2)RR are summarized,which provides directions for the future development of this field.It is concluded that plasmonic catalysts exhibit potential capabilities in enhancing CO_(2)RR while more in situ techniques are essential to further clarify the inner mechanisms.展开更多
For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator（DMG SSOI） MOSFETs is deve...For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator（DMG SSOI） MOSFETs is developed.We investigate the improved short channel effect（SCE）,hot carrier effect（HCE）,drain-induced barrier-lowering（DIBL） and carrier transport efficiency for the novel structure MOSFET.The analytical model takes into account the effects of different metal gate lengths,work functions,the drain bias and Ge mole fraction in the relaxed SiGe buffer.The surface potential in the channel region exhibits a step potential,which can suppress SCE,HCE and DIBL.Also,strained-Si and SOI structure can improve the carrier transport efficiency,with strained-Si being particularly effective.Further, the threshold voltage model correctly predicts a＂rollup＂in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer.The validity of the two-dimensional analytical model is verified using numerical simulations.展开更多
文摘Hot carrier induced (HCI) degradation of surface channel n MOSFETs with different oxide thicknesses is investigated under maximum substrate current condition.Results show that the key parameters m and n of Hu's lifetime prediction model have a close relationship with oxide thickness.Furthermore,a linear relationship is found between m and n .Based on this result,the lifetime prediction model can be expended to the device with thinner oxides.
基金Project supported by the Key Program of the National Natural Science Foundation of China(No.60836004)the Ministry of Education Creative Team Research Project,China.
文摘Hot carrier effect（HCE） is studied on annular NMOS and two-edged NMOS such as H-shape gate NMOS, T-shape gate NMOS and common two-edged NMOS.Based on the chemical reaction equation of HCE degradation and a geometry dependent reaction diffusion equation,a HCE degradation model for annular NMOS and two-edged NMOS is proposed.According to this model,we conclude that the time exponent of the threshold voltage degradation depends on the configuration of the gate,and annular NMOS has more serious HCE degradation than two-edged NMOS.The design,fabrication and HCE experiments of these NMOS in a 0.5-μm PD SOI process verify the correctness of the conclusion.
文摘Hot carrier effects of p MOSFETs with different oxide thicknesses are studied in low gate voltage range.All electrical parameters follow a power law relationship with stress time,but degradation slope is dependent on gate voltage.For the devices with thicker oxides,saturated drain current degradation has a close relationship with the product of gate current and electron fluence.For small dimensional devices,saturated drain current degradation has a close relationship with the electron fluence.This degradation model is valid for p MOSFETs with 0 25μm channel length and different gate oxide thicknesses.
文摘The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.
基金supported by the Key Program of the National Natural Science Foundation of China(Grant No.60836004)the National Natural Science Foundation of China(Grant Nos.61006070 and 61076025)
文摘Annular gate nMOSFETs are frequently used in spaceborne integrated circuits due to their intrinsic good capability of resisting total ionizing dose （TID） effect. However, their capability of resisting the hot carrier effect （HCE） has also been proven to be very weak. In this paper, the reason why the annular gate nMOSFETs have good TID but bad HCE resistance is discussed in detail, and an improved design to locate the source contacts only along one side of the annular gate is used to weaken the HCE degradation. The good TID and HCE hardened capability of the design are verified by the experiments for I/O and core nMOSFETs in a 0.18 μm bulk CMOS technology. In addition, the shortcoming of this design is also discussed and the TID and the HCE characteristics of the replacers （the annular source nMOSFETs） are also studied to provide a possible alternative for the designers.
基金Project supported by the National Basic Research Program of China (Grant No. 2011CBA00606)the National Natural Science Foundation of China (Grant No. 61106106)the Fundamental Research Funds for the Central Universities, China (Grant No. K50510250006)
文摘The hot carrier effect （HCE） of an ultra-deep sub-micron p-channel metal–oxide semiconductor field-effect transistor （pMOSFET） is investigated in this paper. Experiments indicate that the generation of positively charged interface states is the predominant mechanism in the case of the ultra-deep sub-micron pMOSFET. The relation of the pMOSFET hot carrier degradation to stress time （t）, channel width （W ）, channel length （L）, and stress voltage （Vd ） is then discussed. Based on the relation, a lifetime prediction model is proposed, which can predict the lifetime of the ultra-deep sub-micron pMOSFET accurately and reflect the influence of the factors on hot carrier degradation directly.
基金Supported by the National Defense Preresearch Fund Program(No.99J8.1.1.DZD132)
文摘Grooved gate structure Metal-Oxide-Semiconductor (MOS) device is consideredas the most promising candidate used in deep and super-deep sub-micron region, for it cansuppress hot carrier effect and short channel effect deeply. Based on the hydrodynamic energytransport model, using two-dimensional device simulator Medici, the relation between structureparameters and hot carrier effect immunity for deep-sub-micron N-channel MOSFET's is studiedand compared with that of counterpart conventional planar device in this paper. The examinedstructure parameters include negative junction depth, concave corner and effective channel length.Simulation results show that grooved gate device can suppress hot carrier effect deeply even indeep sub-micron region. The studies also indicate that hot carrier effect is strongly influencedby the concave corner and channel length for grooved gate device. With the increase of concavecorner, the hot carrier effect in grooved gate MOSFET decreases sharply, and with the reducingof effective channel length, the hot carrier effect becomes large.
文摘A compact model for LDD MOSFET is proposed,which involves the hyperbolic tangent function description and the physics of device with emphasis on the substrate current modeling.The simulation results demonstrate good agreement with measurement,and show that deep submicron LDD MOSFET has larger substrate current than submicron device does.The improved model costs low computation consumption,and is effective in manifestation of hot carrier effect and other effects in deep submicron devices,in turn is suitable for design and reliability analysis of scaling down devices.
基金supported by the National Key R&D Program of China(Grant No.2022YFA1505000)the National Natural Science Foundation of China(Grant No.22072158)the Strategic Priority Research Program of Chinese Academy of Sciences(Grant No.XDB36000000).
文摘Utilizing plasmonic effects to assist electrochemical reactions exhibits a huge potential in tuning the reaction activities and product selectivity,which is most appealing especially in chemical reactions with multiple products,such as CO_(2)reduction reaction(CO_(2)RR).However,a comprehensive review of the development and the underlying mechanisms in plasmon-assisted electrocatalytic CO_(2)RR remains few and far between.Herein,the fundamentals of localized surface plasmonic resonance(LSPR)excitation and the properties of typical plasmonic metals(including Au,Ag,and Cu)are retrospected.Subsequently,the potential mechanisms of plasmonic effects(such as hot carrier effects and photothermal effects)on the reaction performance in the field of plasmon-assisted electrocatalytic CO_(2)RR are summarized,which provides directions for the future development of this field.It is concluded that plasmonic catalysts exhibit potential capabilities in enhancing CO_(2)RR while more in situ techniques are essential to further clarify the inner mechanisms.
基金Project supported by the National Natural Science Foundation of China(Nos.60976068,60936005)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China Program(No.708083)the Specialized Research Fund for the Doctoral Program of Higher Education,China(No.200807010010).
文摘For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator（DMG SSOI） MOSFETs is developed.We investigate the improved short channel effect（SCE）,hot carrier effect（HCE）,drain-induced barrier-lowering（DIBL） and carrier transport efficiency for the novel structure MOSFET.The analytical model takes into account the effects of different metal gate lengths,work functions,the drain bias and Ge mole fraction in the relaxed SiGe buffer.The surface potential in the channel region exhibits a step potential,which can suppress SCE,HCE and DIBL.Also,strained-Si and SOI structure can improve the carrier transport efficiency,with strained-Si being particularly effective.Further, the threshold voltage model correctly predicts a＂rollup＂in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer.The validity of the two-dimensional analytical model is verified using numerical simulations.
