We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO_3/Hf AlO/SiO_2. These proposed materials posse...We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO_3/Hf AlO/SiO_2. These proposed materials possess low valence band offset with high permittivity to improve both the erase speed and retention time in barrier engineered silicon-oxide-nitride-oxide-silicon（BE-SONOS）. In the proposed structure Hf Al O and AlLaO_3 replace Si_3N_4 and the top SiO_2 layer in a conventional oxide/nitride/oxide（ONO） tunnel stack. Due to the lower conduction band offset（CBO） and high permittivity of the proposed material in the tunnel layer, it offers better program/erase（P/E） speed and retention time. In this work the gate length is also scaled down from 220 to 55 nm to observe the effect of high-k materials while scaling, for the same equivalent oxide thickness（EOT）. We found that the scaling down of the gate length has a negligible impact on the memory window of the devices. Hence, various investigated tunnel oxide stacks possess a good memory window with a charge retained up to 87.4%（at room temperature） after a period of ten years. We also examine the use of a metal gate instead of a polysilicon gate, which shows improved P/E speed and retention time.展开更多
文摘We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO_3/Hf AlO/SiO_2. These proposed materials possess low valence band offset with high permittivity to improve both the erase speed and retention time in barrier engineered silicon-oxide-nitride-oxide-silicon（BE-SONOS）. In the proposed structure Hf Al O and AlLaO_3 replace Si_3N_4 and the top SiO_2 layer in a conventional oxide/nitride/oxide（ONO） tunnel stack. Due to the lower conduction band offset（CBO） and high permittivity of the proposed material in the tunnel layer, it offers better program/erase（P/E） speed and retention time. In this work the gate length is also scaled down from 220 to 55 nm to observe the effect of high-k materials while scaling, for the same equivalent oxide thickness（EOT）. We found that the scaling down of the gate length has a negligible impact on the memory window of the devices. Hence, various investigated tunnel oxide stacks possess a good memory window with a charge retained up to 87.4%（at room temperature） after a period of ten years. We also examine the use of a metal gate instead of a polysilicon gate, which shows improved P/E speed and retention time.
