The NBTI degradation phenomenon and the role of hydrogen during NBT stress are presented in this paper. It is found that PBT stress can recover a fraction of Vth shift induced by NBT1. However, this recovery is unstab...The NBTI degradation phenomenon and the role of hydrogen during NBT stress are presented in this paper. It is found that PBT stress can recover a fraction of Vth shift induced by NBT1. However, this recovery is unstable. The original degradation reappears soon after reapplication of the NBT stress condition. Hydrogen-related species play a key role during a device＇s NBT degradation. Experimental results show that the diffusion species are neutral, they repassivate Si dangling bond which is independent of the gate voltage polaxity. In addition to the diffusion towards gate oxide, hydrogen diffusion to Si-substrate must be taken into account for it also has important influence on device degradation during NBT stress.展开更多
This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor （PMOSFET） degradation during negative bias temperature （NBT） stress. When a relatively large g...This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor （PMOSFET） degradation during negative bias temperature （NBT） stress. When a relatively large gate voltage is applied, the degradation magnitude is much more than the drain voltage which is the same as the gate voltage supplied, and the time exponent gets larger than that of the NBT instability （NBTI）. With decreasing drain voltage, the degradation magnitude and the time exponent all get smaller. At some values of the drain voltage, the degradation magnitude is even smaller than that of NBTI, and when the drain voltage gets small enough, the exhibition of degradation becomes very similar to the NBTI degradation. When a relatively large drain voltage is applied, with decreasing gate voltage, the degradation magnitude gets smaller. However, the time exponent becomes larger. With the help of electric field simulation, this paper concludes that the degradation magnitude is determined by the vertical electric field of the oxide, the amount of hot holes generated by the strong channel lateral electric field at the gate/drain overlap region, and the time exponent is mainly controlled by localized damage caused by the lateral electric field of the oxide in the gate/drain overlap region where hot carriers are produced.展开更多
The effect of the static negative bias temperature （NBT） stress on a p-channel power metal-oxide-semiconductor field-effect transistor （MOSFET） is investigated by experiment and simulation. The time evolution of t...The effect of the static negative bias temperature （NBT） stress on a p-channel power metal-oxide-semiconductor field-effect transistor （MOSFET） is investigated by experiment and simulation. The time evolution of the negative bias temperature instability （NBTI） degradation has the trend predicted by the reaction-diffusion （R-D） model but with an exaggerated time scale. The phenomena of the flat-roof section are observed under various stress conditions, which can be considered as the dynamic equilibrium phase in the R-D process. Based on the simulated results, the variation of the flat-roof section with the stress condition can be explained.展开更多
The effect of substrate bias on the degradation during applying a negative bias temperature （NBT） stress is studied in this paper. With a smaller gate voltage stress applied, the degradation of negative bias tempera...The effect of substrate bias on the degradation during applying a negative bias temperature （NBT） stress is studied in this paper. With a smaller gate voltage stress applied, the degradation of negative bias temperature instability （NBTI） is enhanced, and there comes forth an inflexion point. The degradation pace turns larger when the substrate bias is higher than the inflexion point. The substrate hot holes can be injected into oxide and generate additional oxide traps, inducing an inflexion phenomenon. When a constant substrate bias stress is applied, as the gate voltage stress increases, an inflexion comes into being also. The higher gate voltage causes the electrons to tunnel into the substrate from the poly, thereby generating the electro,hole pairs by impact ionization. The holes generated by impact ionization and the holes from the substrate all can be accelerated to high energies by the substrate bias. More additional oxide traps can be produced, and correspondingly, the degradation is strengthened by the substrate bias. The results of the alternate stress experiment show that the interface traps generated by the hot holes cannot be annealed, which is different from those generated by common holes.展开更多
Hot carrier injection （HCI） at high temperatures and different values of gate bias Vg has been performed in order to study the actions of negative bias temperature instability （NBTI） and hot carriers. Hot-carrier-...Hot carrier injection （HCI） at high temperatures and different values of gate bias Vg has been performed in order to study the actions of negative bias temperature instability （NBTI） and hot carriers. Hot-carrier-stress-induced damage at Vg = Vd, where Vd is the voltage of the transistor drain, increases as temperature rises, contrary to conventional hot carrier behaviour, which is identified as being related to the NBTI. A comparison between the actions of NBTI and hot carriers at low and high gate voltages shows that the damage behaviours are quite different： the low gate voltage stress results in an increase in transconductance, while the NBTI-dominated high gate voltage and high temperature stress causes a decrease in transconductance. It is concluded that this can be a major source of hot carrier damage at elevated temperatures and high gate voltage stressing of p-channel metal-oxide-semiconductor field-effect transistors （PMOSFETs）. We demonstrate a novel mode of NBTI-enhanced hot carrier degradation in PMOSFETs. A novel method to decouple the actions of NBTI from that of hot carriers is also presented.展开更多
A new on-line methodology is used to characterize the negative bias temperature instability （NBTI） without inherent recovery. Saturation drain voltage shift and mobility shift are extracted by ID-VD characterization...A new on-line methodology is used to characterize the negative bias temperature instability （NBTI） without inherent recovery. Saturation drain voltage shift and mobility shift are extracted by ID-VD characterizations, which were measured before stress, and after every certain stress phase, using the proportional differential operator （PDO） method. The new on-line methodology avoids the mobility linearity assumption as compared with the previous onthe-fly method. It is found that both reaction-diffusion and charge-injection processes are important in NBTI effect under either DC or AC stress. A similar activation energy, 0.15 eV, occurred in both DC and AC NBTI processes. Also degradation rate factor is independent of temperature below 90℃ and sharply increases above it. The frequency dependence of NBTI degradation shows that NBTI degradation is independent of frequencies. The carrier tunnelling and reaction-diffusion mechanisms exist simultaneously in NBTI degradation of sub-micron pMOSFETs, and the carrier tunnelling dominates the earlier NBTI stage and the reaction-diffusion mechanism follows when the generation rate of traps caused by carrier tunnelling reaches its maximum.展开更多
This paper studies negative bias temperature instability （NBTI） under alternant and alternating current （AC） stress. Under alternant stress, the degradation smaller than that of single negative stress is obtained....This paper studies negative bias temperature instability （NBTI） under alternant and alternating current （AC） stress. Under alternant stress, the degradation smaller than that of single negative stress is obtained. The smaller degradation is resulted from the recovery of positive stress. There are two reasons for the recovery. One is the passivation of H dangling bonds, and another is the detrapping of charges trapped in the oxide. Under different frequencies of AC stress, the parameters all show regular degradation, and also smaller than that of the direct current stress. The higher the frequency is, the smaller the degradation becomes. As the negative stress time is too small under higher frequency, the deeper defects are hard to be filled in. Therefore, the detrapping of oxide charges is easy to occur under positive bias and the degradation is smaller with higher frequency.展开更多
The exponent n of the generation of an interface trap （Nit）, which contributes to the power-law negative bias temperature instability （NBTI） degradation, and the exponent’s time evolution are investigated by simu...The exponent n of the generation of an interface trap （Nit）, which contributes to the power-law negative bias temperature instability （NBTI） degradation, and the exponent’s time evolution are investigated by simulations with varying the stress voltage Vg and temperature T. It is found that the exponent n in the diffusion-limited phase of the degradation process is irrelevant to both Vg and T. The time evolution of the exponent n is affected by the stress conditions, which is reflected in the shift of the onset of the diffusion-limited phase. According to the diffusion profiles, the generation of the atomic hydrogen species, which is equal to the buildup of Nit, is strongly correlated with the stress conditions, whereas the diffusion of the hydrogen species shows Vg-unaffected but T-affected relations through the normalized results.展开更多
The effect of negative bias temperature instability （NBTI） on a single event transient （SET） has been studied in a 130 nm bulk silicon CMOS process based on 3D TCAD device simulations. The investigation shows that...The effect of negative bias temperature instability （NBTI） on a single event transient （SET） has been studied in a 130 nm bulk silicon CMOS process based on 3D TCAD device simulations. The investigation shows that NBTI can result in the pulse width and amplitude of SET narrowing when the heavy ion hits the PMOS in the high-input inverter; but NBTI can result in the pulse width and amplitude of SET broadening when the heavy ion hits the NMOS in the low-input inverter. Based on this study, for the first time we propose that the impact of NBTI on a SET produced by the heavy ion hitting the NMOS has already been a significant reliability issue and should be of wide concern, and the radiation hardened design must consider the impact of NBTI on a SET.展开更多
An analytical model is proposed to calculate single event transient (SET) pulse width with bulk complementary metal oxide semiconductor (CMOS) technology based on the physics of semiconductor devices. Combining with t...An analytical model is proposed to calculate single event transient (SET) pulse width with bulk complementary metal oxide semiconductor (CMOS) technology based on the physics of semiconductor devices. Combining with the most prevalent negative bias temperature instability (NBTI) degradation model, a novel analytical model is developed to predict the time evolution of the NBTI induced SET broadening in the production, and NBTI experiments and three-dimensional numerical device simulations are used to verify the model. At the same time, an analytical model to predict the time evolution of the NBTI induced SET broadening in the propagation is also proposed, and NBTI experiments and the simulation program with integrated circuit emphasis (SPICE) are used to verify the proposed model.展开更多
Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing ga...Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing gate oxide defects(ΔV_(HT)),and the generation of gate oxide defects(ΔV_(OT)).In this work,the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate(HKMG)process is thoroughly studied.The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature.The effects of the three underlying subcomponents are evaluated by using the comprehensive models.It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress.Moreover,the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted.The dependence of operating lifetime on stress bias and temperature is also discussed.It is observed that NBTI lifetime significantly decreases as the stress increases.Furthermore,the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.展开更多
In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal-oxide semiconductor field-effect transistors（VDMOSFETs） subjected to negative bias tempe...In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal-oxide semiconductor field-effect transistors（VDMOSFETs） subjected to negative bias temperature（NBT）stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps（permanent component）.Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.展开更多
Negative bias temperature instability（NBTI） has become a serious reliability issue, and the interface traps and oxide charges play an important role in the degradation process. In this paper, we study the recovery o...Negative bias temperature instability（NBTI） has become a serious reliability issue, and the interface traps and oxide charges play an important role in the degradation process. In this paper, we study the recovery of NBTI systemically under different conditions in the P-type metal–oxide–semiconductor field effect transistor（PMOSFET）, explain the various recovery phenomena, and find the possible processes of the recovery.展开更多
Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature （NBT-PBT-NBT） stress conditions are investigated in this paper. It is found that for all de...Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature （NBT-PBT-NBT） stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.展开更多
The impact of negative bias temperature instability （NBTI） can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps （△ VHT） in gate insulator, generated traps （△ VOT...The impact of negative bias temperature instability （NBTI） can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps （△ VHT） in gate insulator, generated traps （△ VOT） in bulk insulator, and interface trap generation （△ VIT）. In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal-oxide semiconductor （CMOS） process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction-diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.展开更多
A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power ga...A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM). The experiment results show that PBTI has significant influence on the read and write operations of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 106 s working time. Then, a circuit level simulation was used to verify the assumption of the SPAP model, and finally the statistic data of CPU2000 benchmarks show that the proposed model has a reduction of 3.85% for estimation of the SNM degradation after 106 s working time compared with previous work.展开更多
The influence of PMOSFET gate length on the parameter degradation relations under negative bias temperature insta- bility （NBTI） stress is studied. The threshold voltage degradation increases with reducing the gate ...The influence of PMOSFET gate length on the parameter degradation relations under negative bias temperature insta- bility （NBTI） stress is studied. The threshold voltage degradation increases with reducing the gate length. By calculating the relations between the threshold voltage and the linear/saturation drain current, we obtain their correlation coefficients. Comparing the test result with the calculated linear/saturation current value, we obtain the ratio factors. The ratio factors decrease differently when the gate length diminishes. When the gate length reduces to some degree, the linear ratio factor decreases from greater than 1 to nearly 1, but the saturation factor decreases from greater than l to smaller than 1. This results from the influence of mobility and the velocity saturation effect. Moreover, due to the un-uniform distribution of potential damages along the channel, the descending slopes of the curve are different.展开更多
In wireless sensor network （WSN）, the communication node is the heart of the whole system. Negative bias temperature instability （NBTI） is becoming one of the most important factors that decide the life time of no...In wireless sensor network （WSN）, the communication node is the heart of the whole system. Negative bias temperature instability （NBTI） is becoming one of the most important factors that decide the life time of node chips, especially with the feature size declining. In this paper, the NBTI impact on the front-end circuits in the WSN nodes is studied, such as voltage-controlled oscillator （VCO）, charge pump （CP）, low noise amplifier （LNA）, and even the whole transceiver system. The circuit level NBTI degeneration models are built for the key modules and the entire transceiver. It is shown that the phase noise of the VCO will be deteriorated, the current mismatch of the CP and the noise figure of the LNA will both be increased, and the sensitivity and the adjacent channel selectivity （ACS） will be depressed by NBTI. The conclusions are proved by simulation results using HJTC 0.18 μm technology.展开更多
As semiconductor manufacturing migrates to more advanced technology nodes, accelerated aging effect for nanoscale devices poses as a key challenge for designers to find countermeasures that effectively mitigate the de...As semiconductor manufacturing migrates to more advanced technology nodes, accelerated aging effect for nanoscale devices poses as a key challenge for designers to find countermeasures that effectively mitigate the degradation and prolong system's lifetime. Negative Bias Temperature Instability (NBTI) is emerging as one of the major reliability concerns. Two software tools for NBTI analyzing are proposed in this paper, one for transistor-level, and the other for gate-level. The transistor-level can be used to estimate the delay degradation due to NBTI effect very accurately, while the gate-level can be used for repeat analysis in circuit optimization because of its fast computing speed.展开更多
A simple standard reaction-diffusion（RD） model assumes an infinite oxide thickness and a zero initial interface trap density, which is not the case in real MOS devices.In this paper, we numerically solve the RD mode...A simple standard reaction-diffusion（RD） model assumes an infinite oxide thickness and a zero initial interface trap density, which is not the case in real MOS devices.In this paper, we numerically solve the RD model by taking into account the finite oxide thickness and an initial trap density.The results show that trap generation/ passivation as a function of stress/recovery time is strongly affected by the condition of the gate-oxide/poly-Si boundary.When an absorbent boundary is considered, the RD model is more consistent with the measured interfacetrap data from CMOS devices under bias temperature stress.The results also show that non-negligible initial traps should affect the power index n when a power law of the trap generation with the stress time, tn, is observed in the diffusion limited region of the RD model.展开更多
基金Project supported by the National Natural Science Foundation of China （Grant No 60206006）, the Hi-Tech Research ＆ Development Program of China （Grant No 2004AA1Z1070） and the Key Project of Chinese Ministry of Education （Grant No 104172）.
文摘The NBTI degradation phenomenon and the role of hydrogen during NBT stress are presented in this paper. It is found that PBT stress can recover a fraction of Vth shift induced by NBT1. However, this recovery is unstable. The original degradation reappears soon after reapplication of the NBT stress condition. Hydrogen-related species play a key role during a device＇s NBT degradation. Experimental results show that the diffusion species are neutral, they repassivate Si dangling bond which is independent of the gate voltage polaxity. In addition to the diffusion towards gate oxide, hydrogen diffusion to Si-substrate must be taken into account for it also has important influence on device degradation during NBT stress.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60736033 and 60376024)the National Key Technology Research and Development Program of the Ministry of Science and Technology of China (Grant No. 2007BAK25B03)
文摘This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor （PMOSFET） degradation during negative bias temperature （NBT） stress. When a relatively large gate voltage is applied, the degradation magnitude is much more than the drain voltage which is the same as the gate voltage supplied, and the time exponent gets larger than that of the NBT instability （NBTI）. With decreasing drain voltage, the degradation magnitude and the time exponent all get smaller. At some values of the drain voltage, the degradation magnitude is even smaller than that of NBTI, and when the drain voltage gets small enough, the exhibition of degradation becomes very similar to the NBTI degradation. When a relatively large drain voltage is applied, with decreasing gate voltage, the degradation magnitude gets smaller. However, the time exponent becomes larger. With the help of electric field simulation, this paper concludes that the degradation magnitude is determined by the vertical electric field of the oxide, the amount of hot holes generated by the strong channel lateral electric field at the gate/drain overlap region, and the time exponent is mainly controlled by localized damage caused by the lateral electric field of the oxide in the gate/drain overlap region where hot carriers are produced.
基金Project supported by the National Basic Research Program of China(Grant No.2011CBA00606)the National Natural Science Foundation of China(Grant No.61106106)
文摘The effect of the static negative bias temperature （NBT） stress on a p-channel power metal-oxide-semiconductor field-effect transistor （MOSFET） is investigated by experiment and simulation. The time evolution of the negative bias temperature instability （NBTI） degradation has the trend predicted by the reaction-diffusion （R-D） model but with an exaggerated time scale. The phenomena of the flat-roof section are observed under various stress conditions, which can be considered as the dynamic equilibrium phase in the R-D process. Based on the simulated results, the variation of the flat-roof section with the stress condition can be explained.
基金Project supported by the National Natural Science Foundation of China (Grant Nos 60376024,60736033 and 60506020)the National High Technology Research and Development Program of China (Grant No 2003AA1Z1630)
文摘The effect of substrate bias on the degradation during applying a negative bias temperature （NBT） stress is studied in this paper. With a smaller gate voltage stress applied, the degradation of negative bias temperature instability （NBTI） is enhanced, and there comes forth an inflexion point. The degradation pace turns larger when the substrate bias is higher than the inflexion point. The substrate hot holes can be injected into oxide and generate additional oxide traps, inducing an inflexion phenomenon. When a constant substrate bias stress is applied, as the gate voltage stress increases, an inflexion comes into being also. The higher gate voltage causes the electrons to tunnel into the substrate from the poly, thereby generating the electro,hole pairs by impact ionization. The holes generated by impact ionization and the holes from the substrate all can be accelerated to high energies by the substrate bias. More additional oxide traps can be produced, and correspondingly, the degradation is strengthened by the substrate bias. The results of the alternate stress experiment show that the interface traps generated by the hot holes cannot be annealed, which is different from those generated by common holes.
基金Project supported by the National Natural Science Foundation of China （Grant No 60206006）. the Program for New Century Excellent Talents of Ministry of Education of China （Grant No 681231366）. the National Defense Pre-Research Foundation of China （Grant No 51408010305DZ0168） and the Key Project of Chinese Ministry of Education （Grant No 104172）.
文摘Hot carrier injection （HCI） at high temperatures and different values of gate bias Vg has been performed in order to study the actions of negative bias temperature instability （NBTI） and hot carriers. Hot-carrier-stress-induced damage at Vg = Vd, where Vd is the voltage of the transistor drain, increases as temperature rises, contrary to conventional hot carrier behaviour, which is identified as being related to the NBTI. A comparison between the actions of NBTI and hot carriers at low and high gate voltages shows that the damage behaviours are quite different： the low gate voltage stress results in an increase in transconductance, while the NBTI-dominated high gate voltage and high temperature stress causes a decrease in transconductance. It is concluded that this can be a major source of hot carrier damage at elevated temperatures and high gate voltage stressing of p-channel metal-oxide-semiconductor field-effect transistors （PMOSFETs）. We demonstrate a novel mode of NBTI-enhanced hot carrier degradation in PMOSFETs. A novel method to decouple the actions of NBTI from that of hot carriers is also presented.
文摘A new on-line methodology is used to characterize the negative bias temperature instability （NBTI） without inherent recovery. Saturation drain voltage shift and mobility shift are extracted by ID-VD characterizations, which were measured before stress, and after every certain stress phase, using the proportional differential operator （PDO） method. The new on-line methodology avoids the mobility linearity assumption as compared with the previous onthe-fly method. It is found that both reaction-diffusion and charge-injection processes are important in NBTI effect under either DC or AC stress. A similar activation energy, 0.15 eV, occurred in both DC and AC NBTI processes. Also degradation rate factor is independent of temperature below 90℃ and sharply increases above it. The frequency dependence of NBTI degradation shows that NBTI degradation is independent of frequencies. The carrier tunnelling and reaction-diffusion mechanisms exist simultaneously in NBTI degradation of sub-micron pMOSFETs, and the carrier tunnelling dominates the earlier NBTI stage and the reaction-diffusion mechanism follows when the generation rate of traps caused by carrier tunnelling reaches its maximum.
基金Project supported by the National Key Science and Technology Special Project,China (Grant No. 2008ZX01002-002)the Fundamental Research Funds for the Central Universities,China (Grant No. JY10000904009)the Major Program and State Key Program of the National Natural Science Foundation of China (Grant Nos. 60890191 and 60736033)
文摘This paper studies negative bias temperature instability （NBTI） under alternant and alternating current （AC） stress. Under alternant stress, the degradation smaller than that of single negative stress is obtained. The smaller degradation is resulted from the recovery of positive stress. There are two reasons for the recovery. One is the passivation of H dangling bonds, and another is the detrapping of charges trapped in the oxide. Under different frequencies of AC stress, the parameters all show regular degradation, and also smaller than that of the direct current stress. The higher the frequency is, the smaller the degradation becomes. As the negative stress time is too small under higher frequency, the deeper defects are hard to be filled in. Therefore, the detrapping of oxide charges is easy to occur under positive bias and the degradation is smaller with higher frequency.
基金Project supported by the National Basic Research Program of China(Grant No.2011CBA00606)the National Natural Science Foundation of China(Grant No.61106106)the Fundamental Research Funds for the Central Universities,China(Grant No.K50511250008)
文摘The exponent n of the generation of an interface trap （Nit）, which contributes to the power-law negative bias temperature instability （NBTI） degradation, and the exponent’s time evolution are investigated by simulations with varying the stress voltage Vg and temperature T. It is found that the exponent n in the diffusion-limited phase of the degradation process is irrelevant to both Vg and T. The time evolution of the exponent n is affected by the stress conditions, which is reflected in the shift of the onset of the diffusion-limited phase. According to the diffusion profiles, the generation of the atomic hydrogen species, which is equal to the buildup of Nit, is strongly correlated with the stress conditions, whereas the diffusion of the hydrogen species shows Vg-unaffected but T-affected relations through the normalized results.
基金Project supported by the Key Program of the National Natural Science Foundation of China(No.60836004)the National Natural Science Foundation of China(Nos.61006070,61076025)
文摘The effect of negative bias temperature instability （NBTI） on a single event transient （SET） has been studied in a 130 nm bulk silicon CMOS process based on 3D TCAD device simulations. The investigation shows that NBTI can result in the pulse width and amplitude of SET narrowing when the heavy ion hits the PMOS in the high-input inverter; but NBTI can result in the pulse width and amplitude of SET broadening when the heavy ion hits the NMOS in the low-input inverter. Based on this study, for the first time we propose that the impact of NBTI on a SET produced by the heavy ion hitting the NMOS has already been a significant reliability issue and should be of wide concern, and the radiation hardened design must consider the impact of NBTI on a SET.
基金supported by the Key Program of the National Natural Science Foundation of China (Grant No. 60836004)the National Natural Science Foundation of China (Grant Nos. 61006070, 61076025)
文摘An analytical model is proposed to calculate single event transient (SET) pulse width with bulk complementary metal oxide semiconductor (CMOS) technology based on the physics of semiconductor devices. Combining with the most prevalent negative bias temperature instability (NBTI) degradation model, a novel analytical model is developed to predict the time evolution of the NBTI induced SET broadening in the production, and NBTI experiments and three-dimensional numerical device simulations are used to verify the model. At the same time, an analytical model to predict the time evolution of the NBTI induced SET broadening in the propagation is also proposed, and NBTI experiments and the simulation program with integrated circuit emphasis (SPICE) are used to verify the proposed model.
文摘Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing gate oxide defects(ΔV_(HT)),and the generation of gate oxide defects(ΔV_(OT)).In this work,the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate(HKMG)process is thoroughly studied.The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature.The effects of the three underlying subcomponents are evaluated by using the comprehensive models.It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress.Moreover,the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted.The dependence of operating lifetime on stress bias and temperature is also discussed.It is observed that NBTI lifetime significantly decreases as the stress increases.Furthermore,the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.
基金Project supported by the Fund from the Ministry of Education,Science and Technological Development of the Republic of Serbia(Grant Nos.OI-171026 and TR-32026)the Ei PCB Factory,Ni
文摘In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal-oxide semiconductor field-effect transistors（VDMOSFETs） subjected to negative bias temperature（NBT）stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps（permanent component）.Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.
基金Project supported by the National Basic Research Program of China(Grant No.2011CBA00606)the National Natural Science Foundation of China(Grant Nos.61404097,61334002,61106106,and 61176130)the Fundamental Research Funds for the Central Universities,China(Grant No.JB140415)
文摘Negative bias temperature instability（NBTI） has become a serious reliability issue, and the interface traps and oxide charges play an important role in the degradation process. In this paper, we study the recovery of NBTI systemically under different conditions in the P-type metal–oxide–semiconductor field effect transistor（PMOSFET）, explain the various recovery phenomena, and find the possible processes of the recovery.
基金Project supported by the National Natural Science Foundation of China （Grant No 60206006）, the Program for New Century Excellent Talents of Ministry of Education of China （Grant No 681231366）, the National Defense Pre-Research Foundation of China （Grant No 51308040103） and the Key Project of Chinese Ministry of Education （Grant No 104172）.
文摘Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature （NBT-PBT-NBT） stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.
基金supported by the National Natural Science Foundation of China(Grant Nos.61574056 and 61204038)the Natural Science Funds of Shanghai,China(Grant No.14ZR1412000)+1 种基金the Fund from the Science and Technology Commission of Shanghai Municipality(Grant No.14DZ2260800)Shanghai Sailing Program(Grant No.17YF1404700)
文摘The impact of negative bias temperature instability （NBTI） can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps （△ VHT） in gate insulator, generated traps （△ VOT） in bulk insulator, and interface trap generation （△ VIT）. In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal-oxide semiconductor （CMOS） process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction-diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.
基金Projects(60873016, 61170083) supported by the National Natural Science Foundation of ChinaProject(20114307110001) supported by the Doctoral Fund of Ministry of Education of China
文摘A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM). The experiment results show that PBTI has significant influence on the read and write operations of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 106 s working time. Then, a circuit level simulation was used to verify the assumption of the SPAP model, and finally the statistic data of CPU2000 benchmarks show that the proposed model has a reduction of 3.85% for estimation of the SNM degradation after 106 s working time compared with previous work.
基金supported by the National Basic Research Program of China(Grant No.2011CBA00606)the National Natural Science Foundation of China(Grant Nos.61334002,61106106,and 61176130)the Fundamental Research Fund for the Central Universities of China(Grant No.JB140415)
文摘The influence of PMOSFET gate length on the parameter degradation relations under negative bias temperature insta- bility （NBTI） stress is studied. The threshold voltage degradation increases with reducing the gate length. By calculating the relations between the threshold voltage and the linear/saturation drain current, we obtain their correlation coefficients. Comparing the test result with the calculated linear/saturation current value, we obtain the ratio factors. The ratio factors decrease differently when the gate length diminishes. When the gate length reduces to some degree, the linear ratio factor decreases from greater than 1 to nearly 1, but the saturation factor decreases from greater than l to smaller than 1. This results from the influence of mobility and the velocity saturation effect. Moreover, due to the un-uniform distribution of potential damages along the channel, the descending slopes of the curve are different.
基金supported in party by the National Key Technological Program of China under Grant No.2008ZX01035-001supported by National Natural Science Foundation of China under Grant No.60870001
文摘In wireless sensor network （WSN）, the communication node is the heart of the whole system. Negative bias temperature instability （NBTI） is becoming one of the most important factors that decide the life time of node chips, especially with the feature size declining. In this paper, the NBTI impact on the front-end circuits in the WSN nodes is studied, such as voltage-controlled oscillator （VCO）, charge pump （CP）, low noise amplifier （LNA）, and even the whole transceiver system. The circuit level NBTI degeneration models are built for the key modules and the entire transceiver. It is shown that the phase noise of the VCO will be deteriorated, the current mismatch of the CP and the noise figure of the LNA will both be increased, and the sensitivity and the adjacent channel selectivity （ACS） will be depressed by NBTI. The conclusions are proved by simulation results using HJTC 0.18 μm technology.
基金Supported by the National Key Technological Program of China (No.2008ZX01035-001)the National Natural Sci-ence Foundation of China (No.60870001)TNList Cross-discipline Fundation
文摘As semiconductor manufacturing migrates to more advanced technology nodes, accelerated aging effect for nanoscale devices poses as a key challenge for designers to find countermeasures that effectively mitigate the degradation and prolong system's lifetime. Negative Bias Temperature Instability (NBTI) is emerging as one of the major reliability concerns. Two software tools for NBTI analyzing are proposed in this paper, one for transistor-level, and the other for gate-level. The transistor-level can be used to estimate the delay degradation due to NBTI effect very accurately, while the gate-level can be used for repeat analysis in circuit optimization because of its fast computing speed.
基金supported by the Micro/Nanoelectronics Science & Technology Innovation Platform,Fudan University
文摘A simple standard reaction-diffusion（RD） model assumes an infinite oxide thickness and a zero initial interface trap density, which is not the case in real MOS devices.In this paper, we numerically solve the RD model by taking into account the finite oxide thickness and an initial trap density.The results show that trap generation/ passivation as a function of stress/recovery time is strongly affected by the condition of the gate-oxide/poly-Si boundary.When an absorbent boundary is considered, the RD model is more consistent with the measured interfacetrap data from CMOS devices under bias temperature stress.The results also show that non-negligible initial traps should affect the power index n when a power law of the trap generation with the stress time, tn, is observed in the diffusion limited region of the RD model.
