In this work,a novel one-time-programmable memory unit based on a Schottky-type p-GaN diode is proposed.During the programming process,the junction switches from a high-resistance state to a low-resistance state throu...In this work,a novel one-time-programmable memory unit based on a Schottky-type p-GaN diode is proposed.During the programming process,the junction switches from a high-resistance state to a low-resistance state through Schottky junction breakdown,and the state is permanently preserved.The memory unit features a current ratio of more than 10^(3),a read voltage window of 6 V,a programming time of less than 10^(−4)s,a stability of more than 108 read cycles,and a lifetime of far more than 10 years.Besides,the fabrication of the device is fully compatible with commercial Si-based GaN process platforms,which is of great significance for the realization of low-cost read-only memory in all-GaN integration.展开更多
A 32 kbit OTP(one-time programmable)memory for MCUs(micro-controller units)used in remote controllers was designed.This OTP memory is used for program and data storage.It is required to apply 5.5V to BL(bit-line)and 1...A 32 kbit OTP(one-time programmable)memory for MCUs(micro-controller units)used in remote controllers was designed.This OTP memory is used for program and data storage.It is required to apply 5.5V to BL(bit-line)and 11V to WL(word-line)for a OTP cell of 0.35μm ETOX(EEPROM tunnel oxide)type by MagnaChip.We use 5V transistors on column data paths to reduce the area of column data paths since they require small areas.In addition,we secure device reliability by using HV(high-voltage)transistors in the WL driver.Furthermore,we change from a static logic to a dynamic logic used for the WL driver in the core circuit.Also,we optimize the WD(write data)switch circuit.Thus,we can implement them with a small-area design.In addition,we implement the address predecoder with a small-area logic circuit.The area of the designed 32 kbit OTP with 5V and HV devices is 674.725μm×258.75μm(=0.1745mm2)and is 56.3% smaller than that using 3.3V devices.展开更多
A differential paired eFuse OTP(one-time programmable)memory cell which can be configured into a 2D(two-dimensional)eFuse cell array was proposed.The sensible resistance of a programmed eFuse link is a half smaller th...A differential paired eFuse OTP(one-time programmable)memory cell which can be configured into a 2D(two-dimensional)eFuse cell array was proposed.The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage.With this 2D array of differential paired eFuse OTP memory cells,we design a 32-bit eFuse OTP memory IP.We use a sense amplifier based D F/F circuit as the BL(bit-line)SA(sense amplifier)and design a sensing margin test circuit with a variable pull-up load.It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.展开更多
基于300 mm 0.18μm MS 5 V工艺平台设计并流片了1k×16一次性可编程OTP器件,并对存储单元的结构、工作原理及工艺等可能影响数据保持寿命的因素进行了分析。根据Arrhenius寿命模型对不同样品设置了高温老化实验测试,收集数据并对OT...基于300 mm 0.18μm MS 5 V工艺平台设计并流片了1k×16一次性可编程OTP器件,并对存储单元的结构、工作原理及工艺等可能影响数据保持寿命的因素进行了分析。根据Arrhenius寿命模型对不同样品设置了高温老化实验测试,收集数据并对OTP器件的保持特性进行建模。通过225℃、250℃和275℃条件下的高温老化加速实验,拟合样品最大数据保持时间曲线。在生产过程中可能出现的最差产品条件下,对1/(kT)与数据保持时间曲线进行数学拟合,计算在不同失效条件下的浮栅电荷泄漏的激活能和最大数据保持时间。展开更多
基金supported in part by the National Key Research and Development Program of China under Grant 2022YFB3604400in part by the Youth Innovation Promotion Association of Chinese Academy Sciences (CAS)+4 种基金in part by the CAS-Croucher Funding Scheme under Grant CAS22801in part by National Natural Science Foundation of China under Grant 62334012, Grant 62074161, Grant 62004213, Grant U20A20208, and Grant 62304252in part by the Beijing Municipal Science and Technology Commission project under Grant Z201100008420009 and Grant Z211100007921018in part by the University of CASin part by the IMECAS-HKUST-Joint Laboratory of Microelectronics
文摘In this work,a novel one-time-programmable memory unit based on a Schottky-type p-GaN diode is proposed.During the programming process,the junction switches from a high-resistance state to a low-resistance state through Schottky junction breakdown,and the state is permanently preserved.The memory unit features a current ratio of more than 10^(3),a read voltage window of 6 V,a programming time of less than 10^(−4)s,a stability of more than 108 read cycles,and a lifetime of far more than 10 years.Besides,the fabrication of the device is fully compatible with commercial Si-based GaN process platforms,which is of great significance for the realization of low-cost read-only memory in all-GaN integration.
基金Project supported by the Second Stage of Brain Korea 21 Projects,Korea
文摘A 32 kbit OTP(one-time programmable)memory for MCUs(micro-controller units)used in remote controllers was designed.This OTP memory is used for program and data storage.It is required to apply 5.5V to BL(bit-line)and 11V to WL(word-line)for a OTP cell of 0.35μm ETOX(EEPROM tunnel oxide)type by MagnaChip.We use 5V transistors on column data paths to reduce the area of column data paths since they require small areas.In addition,we secure device reliability by using HV(high-voltage)transistors in the WL driver.Furthermore,we change from a static logic to a dynamic logic used for the WL driver in the core circuit.Also,we optimize the WD(write data)switch circuit.Thus,we can implement them with a small-area design.In addition,we implement the address predecoder with a small-area logic circuit.The area of the designed 32 kbit OTP with 5V and HV devices is 674.725μm×258.75μm(=0.1745mm2)and is 56.3% smaller than that using 3.3V devices.
基金Project supported by the Second Stage of Brain Korea 21 Projectssupported by Industrial Strategic Technology Development Program funded by the Ministry of Knowledge Economy (MKE,Korea)(10039239,"Development of Power Management System SoC Supporting Multi-Battery-Cells and Multi-Energy-Sources for Smart Phones and Smart Devices")
文摘A differential paired eFuse OTP(one-time programmable)memory cell which can be configured into a 2D(two-dimensional)eFuse cell array was proposed.The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage.With this 2D array of differential paired eFuse OTP memory cells,we design a 32-bit eFuse OTP memory IP.We use a sense amplifier based D F/F circuit as the BL(bit-line)SA(sense amplifier)and design a sensing margin test circuit with a variable pull-up load.It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.
文摘基于300 mm 0.18μm MS 5 V工艺平台设计并流片了1k×16一次性可编程OTP器件,并对存储单元的结构、工作原理及工艺等可能影响数据保持寿命的因素进行了分析。根据Arrhenius寿命模型对不同样品设置了高温老化实验测试,收集数据并对OTP器件的保持特性进行建模。通过225℃、250℃和275℃条件下的高温老化加速实验,拟合样品最大数据保持时间曲线。在生产过程中可能出现的最差产品条件下,对1/(kT)与数据保持时间曲线进行数学拟合,计算在不同失效条件下的浮栅电荷泄漏的激活能和最大数据保持时间。
