Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping appro...Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.展开更多
CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a bri...CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.展开更多
We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximati...We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.展开更多
Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to abo...Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.展开更多
A multimode interference(MMI)structure is designed to simplify the fabrication of quantum cascade laser(QCL)phase-locked arrays.The MMI geometry is optimized with a sufficient output channel distance to accommodate co...A multimode interference(MMI)structure is designed to simplify the fabrication of quantum cascade laser(QCL)phase-locked arrays.The MMI geometry is optimized with a sufficient output channel distance to accommodate conventional photolithography and wet etching process by which power amplifier array is fabricated without using the complicated two-step etching-regrowth or dry etching technique.The far-field pattern with periodically modulated peaks reveals that the beams from the arrays are phase-locked.Furthermore,the frequency tuning performance of the MMI-based phase-locked arrays is studied using the Littrow-configuration external cavity structure.A wavelength tuning range of more than 60 cm^(−1) is demonstrated,which will eventually realize the high power,frequency tunable,large-scale phase-locked arrays,and their application in spectroscopy.展开更多
There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon...There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.展开更多
Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying freq...Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).展开更多
High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase...High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.展开更多
We report that the Atlantic Multi-Decadal Oscillation (AMO) shows the same phase-locked states of period 2 and 3 years that have been reported in many other climate indices. In addition, we find that the report by Mul...We report that the Atlantic Multi-Decadal Oscillation (AMO) shows the same phase-locked states of period 2 and 3 years that have been reported in many other climate indices. In addition, we find that the report by Muller, Curry et al. of an oscillation in the AMO of 9.1 years is a misinterpretation of a maximum in the Fourier spectrum.展开更多
<div style="text-align:justify;"> We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber re...<div style="text-align:justify;"> We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10<sup>?9</sup> and a dynamic locking accuracy of about 5 × 10<sup>?8</sup> are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on. </div>展开更多
Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a vol...Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a voltage source converter(VSC)to an AC weak grid may cause the converter system to become unstable.In this paper,a phase-shift phaselocked loop(PS-PLL)is proposed wherein a back electromotive force(BEMF)observer is added to the conventional phaselocked loop(PLL).The BEMF observer is used to observe the voltage of the infinite grid in the stationaryαβframe,which avoids the problem of inaccurate observations of the grid voltage in the dq frame that are caused by the output phase angle errors of the PLL.The VSC using the PS-PLL can operate as if it is facing a strong grid,thus enhancing the stability of the VSC-HVDC system.The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL,which makes it easy to implement.In addition,because it is difficult to obtain the exact impedance of the grid,the influence of shortcircuit ratio(SCR)estimation errors on the performance of the PS-PLL is also studied.The effectiveness of the proposed PSPLL is verified by the small-signal stability analysis and timedomain simulation.展开更多
This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objec...This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.展开更多
Active damped LCL-filter-based inverters have been widely used for grid-connected distributed generation(DG) systems. In weak grids, however, the phase-locked loop(PLL) dynamics may detrimentally affect the stability ...Active damped LCL-filter-based inverters have been widely used for grid-connected distributed generation(DG) systems. In weak grids, however, the phase-locked loop(PLL) dynamics may detrimentally affect the stability of grid-connected inverters due to interaction between the PLL and the controller. In order to solve the problem, the impact of PLL dynamics on small-signal stability is investigated for the active damped LCL-filtered grid-connected inverters with capacitor voltage feedback. The system closed-loop transfer function is established based on the Norton equivalent model by taking the PLL dynamics into account. Using an established model, the system stability boundary is identified from the viewpoint of PLL bandwidth and current regulator gain. The accuracy of the ranges of stability for the PLL bandwidth and current regulator gain is verified by both simulation and experimental results.展开更多
In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has b...In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions.Even though a lot of PLLs have been proposed,an overview and comparative analysis of multiple PLLs can be helpful for practical applications.In addition,the weak grid condition is a great challenge for the system.Therefore,this study first presents an overview of the existing PLLs together with their general structures and basic working principles.Depending on the implementation of the phase detector,the PLL can be divided into three categories:power-based PLL(pPLL),orthogonal-signalgenerator-based PLL(OSG-PLL)and adaptive-filter-based PLL(AF-PLL).Then,from the above classification,seven typical single-phase PLLs are selected for further study.Finally,some test results are given,and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.展开更多
In this paper, we propose a scheme for the generation of low phase noise tunable mm-wave signal by bearing two lightwaves in a photodiode. These two lightwaves are made phase coherent by an optoelectronic phase locked...In this paper, we propose a scheme for the generation of low phase noise tunable mm-wave signal by bearing two lightwaves in a photodiode. These two lightwaves are made phase coherent by an optoelectronic phase locked loop. Calculated mm-wave power at a frequency of 60 GHz is found to be -4 dBm.展开更多
The uniform boundedness and existence of a global periodic attractor for a third-order phase-locked loop with general phase detector characteristics and frequency modulation input is proved under some parametric condi...The uniform boundedness and existence of a global periodic attractor for a third-order phase-locked loop with general phase detector characteristics and frequency modulation input is proved under some parametric conditions.展开更多
An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the P...An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the PLL,and,therefore,improves control performances of the disturbed GeCs.Besides,the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions.The unbalanced grid is particularly taken into account for the performance analysis.A tuning approach based on the well-designed PI controller is discussed,which results in a fair comparison with conventional PI-type PLLs.The frequency domain properies are quantitatively analysed with respeet to the control stability and the noises rejection.The frequency domain analysis and simulation results suggesti that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency,while have better ability to atenuate high-frequency measurement noises.The phase margin decreases slightly,but remains acceptable.Finally,experimental tests are conducted with a hybrid power hardwarein-the-loop benchmark,in which balanced/unbalanced cases are both explored.The obtained results prove the effectiveness of ESO based PLLs when applied to the disturbed GeC.展开更多
The Gymnarchus niloticus fish can swim in surging and heaving directions only with a long undulating ribbon fin while keeping its body along almost straight line.These features substantially inspire the design of unde...The Gymnarchus niloticus fish can swim in surging and heaving directions only with a long undulating ribbon fin while keeping its body along almost straight line.These features substantially inspire the design of underwater vessels with high maneuverability and station keeping performance,which is characterized by peculiar vortex structures induced by undulating fin propulsion.To reveal the propulsion mechanism under the evolution of these complex vortex structures,the variation of velocity field with the undulating fin’s wave phase on cross section and mid-sagittal plane at wave amplitude of 85°is investigated by phase-locked digital particle image velocimetry(DPIV).Through experimental flow field images,two typical vortex structures are clearly identified,i.e.,streamwise vortex and crescent vortex,which is further explained by supplemental numerical simulations using large eddy simulation.Vortex characteristic and its evolution on cross sections and mid-sagittal planes is investigated,and its relationship with thrust,heave force is also analyzed.It is found that the two kinds of vortexes induce the main hydrodynamic forces in two directions synchronously,which brings the undulating fin propulsion an extra-ordinal maneuverability.The research will be useful for understanding the potential mechanism of this novel propulsion and is of great application prospect in designing more maneuverable underwater vehicles.展开更多
A control strategy of frequency self-adaptation without phase-locked loop(PLL)underαβstationary reference frame(αβ-SRF)for a VSC-HVDC system is presented to improve the operational performance of the system under ...A control strategy of frequency self-adaptation without phase-locked loop(PLL)underαβstationary reference frame(αβ-SRF)for a VSC-HVDC system is presented to improve the operational performance of the system under severe harmonic distortion conditions.The control strategy helps to eliminate the cross-coupling under dq synchronous reference frame(dq-SRF),and is achieved through two key technologies:1)positive phase sequence(PPS)and negative phase sequence(NPS)fundamental components are extracted from the AC grid voltage with an improved multiple complex coefficient filter(IMCF),and 2)grid instantaneous frequency is rapidly and precisely tracked using a frequency self-adaptation tracking algorithm(FATA)without PLL.The proposed strategy is applied to a point-to-point VSCHVDC system and validated by means of simulations.The results are compared to those with the traditional vector control strategy under dq-SRF.Simulation results illustrate that the proposed strategy results in better system performance than that with the traditional strategy in terms of harmonic suppression under normal and severe operating conditions of the AC system.展开更多
Fast and accurate monitoring of the phase,amplitude,and frequency of the grid voltage is essential for single-phase grid-connected converters.The presence of DC offset in the grid voltage is detrimental to not only gr...Fast and accurate monitoring of the phase,amplitude,and frequency of the grid voltage is essential for single-phase grid-connected converters.The presence of DC offset in the grid voltage is detrimental to not only grid synchronization but also the closed-loop stability of the grid-connected converters.In this paper,a new synchronization method to mitigate the effect of DC offset is presented using arbitrarily delayed signal cancelation(ADSC)in a second-order generalized integrator(SOGI)phase-locked loop(PLL).A frequency-fixed SOGI-based PLL(FFSOGI-PLL)is adopted to ensure better stability and to reduce the complexity compared with other SOGI-based PLLs.A small-signal model of the proposed PLL is derived for the systematic design of proportional-integral(PI)controller gains.The effects of frequency variation and ADSC on the proposed PLL are considered,and correction methods are adopted to accurately estimate grid information.The simulation results are presented,along with comparisons to other single-phase PLLs in terms of settling time,peak frequency,and phase error to validate the proposed PLL.The dynamic performance of the proposed PLL is also experimentally validated.Overall,the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all performance indices,offering an improved solution for precise grid synchronization in single-phase applications.展开更多
基金Project supported by the National Key Research and Development Program of China(Grant Nos.2021YFA0718300 and 2021YFA1400900)the National Natural Science Foundation of China(Grant Nos.11920101004,11934002,and 92365208)+1 种基金Science and Technology Major Project of Shanxi(Grant No.202101030201022)Space Application System of China Manned Space Program.
文摘Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.
基金supported by the Pioneer Hundred Talents Program,Chinese Academy of Sciences.
文摘CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.
基金supported by Key Research Program of Frontier Science,Chinese Academy of Sciences(Grant No.QYZDB-SSW-SLH014)the Yong Scientists Fund of the National Natural Science Foundation of China(Grant No.61205143)
文摘We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.
基金Supported by the Tsinghua National Laboratory for Information Science and Technology(TNList)Cross-Discipline Foundationthe National Science and Technology Major Project(No.2010ZX03006-003-01)
文摘Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.
基金supported by the National Basic Research Program of China(Grant Nos.2018YFA0209103 and 2018YFB2200504)the National Natural Science Foundation of China(Grant Nos.61991430,61774146,61790583,61674144,61774150,and 61805168)+1 种基金the Beijing Municipal Science&Technology Commission,China(Grant No.Z201100004020006)the Key Projects of the Chinese Academy of Sciences(Grant Nos.2018147,YJKYYQ20190002,QYZDJ-SSW-JSC027,and XDB43000000).
文摘A multimode interference(MMI)structure is designed to simplify the fabrication of quantum cascade laser(QCL)phase-locked arrays.The MMI geometry is optimized with a sufficient output channel distance to accommodate conventional photolithography and wet etching process by which power amplifier array is fabricated without using the complicated two-step etching-regrowth or dry etching technique.The far-field pattern with periodically modulated peaks reveals that the beams from the arrays are phase-locked.Furthermore,the frequency tuning performance of the MMI-based phase-locked arrays is studied using the Littrow-configuration external cavity structure.A wavelength tuning range of more than 60 cm^(−1) is demonstrated,which will eventually realize the high power,frequency tunable,large-scale phase-locked arrays,and their application in spectroscopy.
基金supported in part by the National Natural Science Foundation of China(Nos.12005245,12075100,and 11775244)by the Scientific and Technological Innovation Project(No.2020000165)from the Institute of High Energy Physics,Chinese Academy of Sciences+1 种基金partially funded by the Scientific Instrument Development Project of the Chinese Academy of Sciences(No.ZDKYYQ20200007)Youth Innovation Promotion Association of the Chinese Academy of Sciences(No.Y201905).
文摘There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.
文摘Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).
基金This work was supported in part by Lodam A/S and in part by the PSO-ELFORSK Program。
文摘High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.
文摘We report that the Atlantic Multi-Decadal Oscillation (AMO) shows the same phase-locked states of period 2 and 3 years that have been reported in many other climate indices. In addition, we find that the report by Muller, Curry et al. of an oscillation in the AMO of 9.1 years is a misinterpretation of a maximum in the Fourier spectrum.
文摘<div style="text-align:justify;"> We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10<sup>?9</sup> and a dynamic locking accuracy of about 5 × 10<sup>?8</sup> are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on. </div>
基金supported by the National Natural Science Foundation of China(No.51677142)the National Key R&D Program of China(No.2016YFB0900600)。
文摘Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a voltage source converter(VSC)to an AC weak grid may cause the converter system to become unstable.In this paper,a phase-shift phaselocked loop(PS-PLL)is proposed wherein a back electromotive force(BEMF)observer is added to the conventional phaselocked loop(PLL).The BEMF observer is used to observe the voltage of the infinite grid in the stationaryαβframe,which avoids the problem of inaccurate observations of the grid voltage in the dq frame that are caused by the output phase angle errors of the PLL.The VSC using the PS-PLL can operate as if it is facing a strong grid,thus enhancing the stability of the VSC-HVDC system.The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL,which makes it easy to implement.In addition,because it is difficult to obtain the exact impedance of the grid,the influence of shortcircuit ratio(SCR)estimation errors on the performance of the PS-PLL is also studied.The effectiveness of the proposed PSPLL is verified by the small-signal stability analysis and timedomain simulation.
基金supported by the National Natural Science Foundation of China under Grant 62004028,62090041the Science Foundation of Sichuan under Grant 2022NSFSC0927.
文摘This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.
基金supported by Science Foundation for Distinguished Young Scholars of Hebei Province(No.E2016203133)Hundred Excellent Innovation Talents Support Program of Hebei Province(No.SLRC2017059)
文摘Active damped LCL-filter-based inverters have been widely used for grid-connected distributed generation(DG) systems. In weak grids, however, the phase-locked loop(PLL) dynamics may detrimentally affect the stability of grid-connected inverters due to interaction between the PLL and the controller. In order to solve the problem, the impact of PLL dynamics on small-signal stability is investigated for the active damped LCL-filtered grid-connected inverters with capacitor voltage feedback. The system closed-loop transfer function is established based on the Norton equivalent model by taking the PLL dynamics into account. Using an established model, the system stability boundary is identified from the viewpoint of PLL bandwidth and current regulator gain. The accuracy of the ranges of stability for the PLL bandwidth and current regulator gain is verified by both simulation and experimental results.
基金This work is supported in part by the National Natural Science Foundation of China(No.51807089,51877104)in part by the Natural Science Foundation of Jiangsu Province(No.BK20180432).
文摘In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions.Even though a lot of PLLs have been proposed,an overview and comparative analysis of multiple PLLs can be helpful for practical applications.In addition,the weak grid condition is a great challenge for the system.Therefore,this study first presents an overview of the existing PLLs together with their general structures and basic working principles.Depending on the implementation of the phase detector,the PLL can be divided into three categories:power-based PLL(pPLL),orthogonal-signalgenerator-based PLL(OSG-PLL)and adaptive-filter-based PLL(AF-PLL).Then,from the above classification,seven typical single-phase PLLs are selected for further study.Finally,some test results are given,and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.
文摘In this paper, we propose a scheme for the generation of low phase noise tunable mm-wave signal by bearing two lightwaves in a photodiode. These two lightwaves are made phase coherent by an optoelectronic phase locked loop. Calculated mm-wave power at a frequency of 60 GHz is found to be -4 dBm.
基金Project supported by the National Natural Science Foundation of China.
文摘The uniform boundedness and existence of a global periodic attractor for a third-order phase-locked loop with general phase detector characteristics and frequency modulation input is proved under some parametric conditions.
基金This paper was supported by G2elab,Grenoble INP,University Grenoble Alpes,France and School of Engineering,HES-sO,Valais,Switzerlandfunding provided by Haute Ecole Specialisee de Suisse occidentale(HES-SO)
文摘An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the PLL,and,therefore,improves control performances of the disturbed GeCs.Besides,the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions.The unbalanced grid is particularly taken into account for the performance analysis.A tuning approach based on the well-designed PI controller is discussed,which results in a fair comparison with conventional PI-type PLLs.The frequency domain properies are quantitatively analysed with respeet to the control stability and the noises rejection.The frequency domain analysis and simulation results suggesti that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency,while have better ability to atenuate high-frequency measurement noises.The phase margin decreases slightly,but remains acceptable.Finally,experimental tests are conducted with a hybrid power hardwarein-the-loop benchmark,in which balanced/unbalanced cases are both explored.The obtained results prove the effectiveness of ESO based PLLs when applied to the disturbed GeC.
基金Projects supported by the National Natural Science Foundation of China(Grant Nos.51379193,51779233).
文摘The Gymnarchus niloticus fish can swim in surging and heaving directions only with a long undulating ribbon fin while keeping its body along almost straight line.These features substantially inspire the design of underwater vessels with high maneuverability and station keeping performance,which is characterized by peculiar vortex structures induced by undulating fin propulsion.To reveal the propulsion mechanism under the evolution of these complex vortex structures,the variation of velocity field with the undulating fin’s wave phase on cross section and mid-sagittal plane at wave amplitude of 85°is investigated by phase-locked digital particle image velocimetry(DPIV).Through experimental flow field images,two typical vortex structures are clearly identified,i.e.,streamwise vortex and crescent vortex,which is further explained by supplemental numerical simulations using large eddy simulation.Vortex characteristic and its evolution on cross sections and mid-sagittal planes is investigated,and its relationship with thrust,heave force is also analyzed.It is found that the two kinds of vortexes induce the main hydrodynamic forces in two directions synchronously,which brings the undulating fin propulsion an extra-ordinal maneuverability.The research will be useful for understanding the potential mechanism of this novel propulsion and is of great application prospect in designing more maneuverable underwater vehicles.
基金supported by the Science and Technology Project of the State Grid Corporation of China(SGRIZLKJ[2015]457)。
文摘A control strategy of frequency self-adaptation without phase-locked loop(PLL)underαβstationary reference frame(αβ-SRF)for a VSC-HVDC system is presented to improve the operational performance of the system under severe harmonic distortion conditions.The control strategy helps to eliminate the cross-coupling under dq synchronous reference frame(dq-SRF),and is achieved through two key technologies:1)positive phase sequence(PPS)and negative phase sequence(NPS)fundamental components are extracted from the AC grid voltage with an improved multiple complex coefficient filter(IMCF),and 2)grid instantaneous frequency is rapidly and precisely tracked using a frequency self-adaptation tracking algorithm(FATA)without PLL.The proposed strategy is applied to a point-to-point VSCHVDC system and validated by means of simulations.The results are compared to those with the traditional vector control strategy under dq-SRF.Simulation results illustrate that the proposed strategy results in better system performance than that with the traditional strategy in terms of harmonic suppression under normal and severe operating conditions of the AC system.
基金supported by the Deanship of Research at Jordan University of Science and Technology (Grant number:20210333).
文摘Fast and accurate monitoring of the phase,amplitude,and frequency of the grid voltage is essential for single-phase grid-connected converters.The presence of DC offset in the grid voltage is detrimental to not only grid synchronization but also the closed-loop stability of the grid-connected converters.In this paper,a new synchronization method to mitigate the effect of DC offset is presented using arbitrarily delayed signal cancelation(ADSC)in a second-order generalized integrator(SOGI)phase-locked loop(PLL).A frequency-fixed SOGI-based PLL(FFSOGI-PLL)is adopted to ensure better stability and to reduce the complexity compared with other SOGI-based PLLs.A small-signal model of the proposed PLL is derived for the systematic design of proportional-integral(PI)controller gains.The effects of frequency variation and ADSC on the proposed PLL are considered,and correction methods are adopted to accurately estimate grid information.The simulation results are presented,along with comparisons to other single-phase PLLs in terms of settling time,peak frequency,and phase error to validate the proposed PLL.The dynamic performance of the proposed PLL is also experimentally validated.Overall,the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all performance indices,offering an improved solution for precise grid synchronization in single-phase applications.
