Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping appro...Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.展开更多
A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-p...A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.展开更多
CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a bri...CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.展开更多
A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacr...A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.展开更多
There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon...There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.展开更多
Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to abo...Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.展开更多
We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a...We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.展开更多
High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase...High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.展开更多
<div style="text-align:justify;"> We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber re...<div style="text-align:justify;"> We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10<sup>?9</sup> and a dynamic locking accuracy of about 5 × 10<sup>?8</sup> are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on. </div>展开更多
We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximati...We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.展开更多
Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying freq...Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).展开更多
In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points...In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.展开更多
A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage change...A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.展开更多
Conventional sliding-mode observer(SMO)-based grid-voltage observation methods often require a low-pass filter(LPF)to remove high-frequency sliding-mode noise.However,a complicated phase-and amplitude-compensation met...Conventional sliding-mode observer(SMO)-based grid-voltage observation methods often require a low-pass filter(LPF)to remove high-frequency sliding-mode noise.However,a complicated phase-and amplitude-compensation method,which is highly sensitive to the DC-offset,is required.A frequency-adaptive dual second-order generalized integrator(SOGI)can be used to replace the LPF,eliminating the compensation link and the effects of the DC-offset;however,strong coupling is introduced between the front-end SOGI block and back-end phase-locked loop(PLL)block,thereby reducing the dynamic performance.To solve this problem,this study proposes an SMO-based grid-voltage observation method with a frequency-fixed dual SOGI and cross-compensated PLL that can eliminate the frequency coupling between the front-end SOGI block and back-end PLL blocks,thereby increasing its dynamic performance.In this study,the phase and amplitude are compensated simultaneously using the proposed cross-compensation method,achieving an accurate observation of the grid voltage under off-nominal frequencies.An analysis of the small-signal model theoretically verified that the proposed method has good dynamic performance.Finally,the superiority of the proposed method is verified through comparative experiments.展开更多
Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a vol...Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a voltage source converter(VSC)to an AC weak grid may cause the converter system to become unstable.In this paper,a phase-shift phaselocked loop(PS-PLL)is proposed wherein a back electromotive force(BEMF)observer is added to the conventional phaselocked loop(PLL).The BEMF observer is used to observe the voltage of the infinite grid in the stationaryαβframe,which avoids the problem of inaccurate observations of the grid voltage in the dq frame that are caused by the output phase angle errors of the PLL.The VSC using the PS-PLL can operate as if it is facing a strong grid,thus enhancing the stability of the VSC-HVDC system.The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL,which makes it easy to implement.In addition,because it is difficult to obtain the exact impedance of the grid,the influence of shortcircuit ratio(SCR)estimation errors on the performance of the PS-PLL is also studied.The effectiveness of the proposed PSPLL is verified by the small-signal stability analysis and timedomain simulation.展开更多
This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objec...This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.展开更多
Active damped LCL-filter-based inverters have been widely used for grid-connected distributed generation(DG) systems. In weak grids, however, the phase-locked loop(PLL) dynamics may detrimentally affect the stability ...Active damped LCL-filter-based inverters have been widely used for grid-connected distributed generation(DG) systems. In weak grids, however, the phase-locked loop(PLL) dynamics may detrimentally affect the stability of grid-connected inverters due to interaction between the PLL and the controller. In order to solve the problem, the impact of PLL dynamics on small-signal stability is investigated for the active damped LCL-filtered grid-connected inverters with capacitor voltage feedback. The system closed-loop transfer function is established based on the Norton equivalent model by taking the PLL dynamics into account. Using an established model, the system stability boundary is identified from the viewpoint of PLL bandwidth and current regulator gain. The accuracy of the ranges of stability for the PLL bandwidth and current regulator gain is verified by both simulation and experimental results.展开更多
A frequency servo system-on-chip(FS-SoC)featuring output power stabilization technology is introduced in this study for high-precision and miniaturized cesium(Cs)atomic clocks.The proposed power stabilization loop(PSL...A frequency servo system-on-chip(FS-SoC)featuring output power stabilization technology is introduced in this study for high-precision and miniaturized cesium(Cs)atomic clocks.The proposed power stabilization loop(PSL)technique,incorporating an off-chip power detector(PD),ensures that the output power of the FS-SoC remains stable,mitigating the impact of power fluctuations on the atomic clock's stability.Additionally,a one-pulse-per-second(1PPS)is employed to syn-chronize the clock with GPS.Fabricated using 65 nm CMOS technology,the measured phase noise of the FS-SoC stands at-69.5 dBc/Hz@100 Hz offset and-83.9 dBc/Hz@1 kHz offset,accompanied by a power dissipation of 19.7 mW.The Cs atomic clock employing the proposed FS-SoC and PSL obtains an Allan deviation of 1.7×10^(-11) with 1-s averaging time.展开更多
In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has b...In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions.Even though a lot of PLLs have been proposed,an overview and comparative analysis of multiple PLLs can be helpful for practical applications.In addition,the weak grid condition is a great challenge for the system.Therefore,this study first presents an overview of the existing PLLs together with their general structures and basic working principles.Depending on the implementation of the phase detector,the PLL can be divided into three categories:power-based PLL(pPLL),orthogonal-signalgenerator-based PLL(OSG-PLL)and adaptive-filter-based PLL(AF-PLL).Then,from the above classification,seven typical single-phase PLLs are selected for further study.Finally,some test results are given,and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.展开更多
基金Project supported by the National Key Research and Development Program of China(Grant Nos.2021YFA0718300 and 2021YFA1400900)the National Natural Science Foundation of China(Grant Nos.11920101004,11934002,and 92365208)+1 种基金Science and Technology Major Project of Shanxi(Grant No.202101030201022)Space Application System of China Manned Space Program.
文摘Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.
基金The National High Technology Research and Devel-opment Program of China (863Program) (No2001AA312010)
文摘A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.
基金supported by the Pioneer Hundred Talents Program,Chinese Academy of Sciences.
文摘CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.
文摘A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.
基金supported in part by the National Natural Science Foundation of China(Nos.12005245,12075100,and 11775244)by the Scientific and Technological Innovation Project(No.2020000165)from the Institute of High Energy Physics,Chinese Academy of Sciences+1 种基金partially funded by the Scientific Instrument Development Project of the Chinese Academy of Sciences(No.ZDKYYQ20200007)Youth Innovation Promotion Association of the Chinese Academy of Sciences(No.Y201905).
文摘There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.
基金Supported by the Tsinghua National Laboratory for Information Science and Technology(TNList)Cross-Discipline Foundationthe National Science and Technology Major Project(No.2010ZX03006-003-01)
文摘Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.
基金supported by the National Natural Science Foundation of China(Grant No.61307128)the National Basic Research Program of China(GrantNo.2010CB327505)+1 种基金the Specialized Research Found for the Doctoral Program of Higher Education of China(Grant No.20131101120027)the Basic Research Foundation of Beijing Institute of Technology of China(Grant No.20120542015)
文摘We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.
基金This work was supported in part by Lodam A/S and in part by the PSO-ELFORSK Program。
文摘High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.
文摘<div style="text-align:justify;"> We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10<sup>?9</sup> and a dynamic locking accuracy of about 5 × 10<sup>?8</sup> are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on. </div>
基金supported by Key Research Program of Frontier Science,Chinese Academy of Sciences(Grant No.QYZDB-SSW-SLH014)the Yong Scientists Fund of the National Natural Science Foundation of China(Grant No.61205143)
文摘We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.
文摘Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).
基金supported by the National Natural Science Foundation of China(Grant Nos.11773060,11973074,U1831137 and 11703070)National Key Basic Research and Development Program(2018YFA0404702)+1 种基金Shanghai Key Laboratory of Space Navigation and Positioning(3912DZ227330001)the Key Laboratory for Radio Astronomy of CAS。
文摘In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.
文摘A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.
基金Supported by the Outstanding Youth Science Foundation of Henan Province(242300421074)Henan Province Key R&D Project(241111210400,241111242300).
文摘Conventional sliding-mode observer(SMO)-based grid-voltage observation methods often require a low-pass filter(LPF)to remove high-frequency sliding-mode noise.However,a complicated phase-and amplitude-compensation method,which is highly sensitive to the DC-offset,is required.A frequency-adaptive dual second-order generalized integrator(SOGI)can be used to replace the LPF,eliminating the compensation link and the effects of the DC-offset;however,strong coupling is introduced between the front-end SOGI block and back-end phase-locked loop(PLL)block,thereby reducing the dynamic performance.To solve this problem,this study proposes an SMO-based grid-voltage observation method with a frequency-fixed dual SOGI and cross-compensated PLL that can eliminate the frequency coupling between the front-end SOGI block and back-end PLL blocks,thereby increasing its dynamic performance.In this study,the phase and amplitude are compensated simultaneously using the proposed cross-compensation method,achieving an accurate observation of the grid voltage under off-nominal frequencies.An analysis of the small-signal model theoretically verified that the proposed method has good dynamic performance.Finally,the superiority of the proposed method is verified through comparative experiments.
基金supported by the National Natural Science Foundation of China(No.51677142)the National Key R&D Program of China(No.2016YFB0900600)。
文摘Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a voltage source converter(VSC)to an AC weak grid may cause the converter system to become unstable.In this paper,a phase-shift phaselocked loop(PS-PLL)is proposed wherein a back electromotive force(BEMF)observer is added to the conventional phaselocked loop(PLL).The BEMF observer is used to observe the voltage of the infinite grid in the stationaryαβframe,which avoids the problem of inaccurate observations of the grid voltage in the dq frame that are caused by the output phase angle errors of the PLL.The VSC using the PS-PLL can operate as if it is facing a strong grid,thus enhancing the stability of the VSC-HVDC system.The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL,which makes it easy to implement.In addition,because it is difficult to obtain the exact impedance of the grid,the influence of shortcircuit ratio(SCR)estimation errors on the performance of the PS-PLL is also studied.The effectiveness of the proposed PSPLL is verified by the small-signal stability analysis and timedomain simulation.
基金supported by the National Natural Science Foundation of China under Grant 62004028,62090041the Science Foundation of Sichuan under Grant 2022NSFSC0927.
文摘This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.
基金supported by Science Foundation for Distinguished Young Scholars of Hebei Province(No.E2016203133)Hundred Excellent Innovation Talents Support Program of Hebei Province(No.SLRC2017059)
文摘Active damped LCL-filter-based inverters have been widely used for grid-connected distributed generation(DG) systems. In weak grids, however, the phase-locked loop(PLL) dynamics may detrimentally affect the stability of grid-connected inverters due to interaction between the PLL and the controller. In order to solve the problem, the impact of PLL dynamics on small-signal stability is investigated for the active damped LCL-filtered grid-connected inverters with capacitor voltage feedback. The system closed-loop transfer function is established based on the Norton equivalent model by taking the PLL dynamics into account. Using an established model, the system stability boundary is identified from the viewpoint of PLL bandwidth and current regulator gain. The accuracy of the ranges of stability for the PLL bandwidth and current regulator gain is verified by both simulation and experimental results.
基金supported by the National Natural Science Foundation of China under Grant 62034002 and 62374026.
文摘A frequency servo system-on-chip(FS-SoC)featuring output power stabilization technology is introduced in this study for high-precision and miniaturized cesium(Cs)atomic clocks.The proposed power stabilization loop(PSL)technique,incorporating an off-chip power detector(PD),ensures that the output power of the FS-SoC remains stable,mitigating the impact of power fluctuations on the atomic clock's stability.Additionally,a one-pulse-per-second(1PPS)is employed to syn-chronize the clock with GPS.Fabricated using 65 nm CMOS technology,the measured phase noise of the FS-SoC stands at-69.5 dBc/Hz@100 Hz offset and-83.9 dBc/Hz@1 kHz offset,accompanied by a power dissipation of 19.7 mW.The Cs atomic clock employing the proposed FS-SoC and PSL obtains an Allan deviation of 1.7×10^(-11) with 1-s averaging time.
基金This work is supported in part by the National Natural Science Foundation of China(No.51807089,51877104)in part by the Natural Science Foundation of Jiangsu Province(No.BK20180432).
文摘In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions.Even though a lot of PLLs have been proposed,an overview and comparative analysis of multiple PLLs can be helpful for practical applications.In addition,the weak grid condition is a great challenge for the system.Therefore,this study first presents an overview of the existing PLLs together with their general structures and basic working principles.Depending on the implementation of the phase detector,the PLL can be divided into three categories:power-based PLL(pPLL),orthogonal-signalgenerator-based PLL(OSG-PLL)and adaptive-filter-based PLL(AF-PLL).Then,from the above classification,seven typical single-phase PLLs are selected for further study.Finally,some test results are given,and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.
