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Synergistic effect of total ionizing dose on single-event gate rupture in SiC power MOSFETs
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作者 曹荣幸 汪柯佳 +9 位作者 孟洋 李林欢 赵琳 韩丹 刘洋 郑澍 李红霞 蒋煜琪 曾祥华 薛玉雄 《Chinese Physics B》 SCIE EI CAS CSCD 2023年第6期666-672,共7页
The synergistic effect of total ionizing dose(TID) and single event gate rupture(SEGR) in SiC power metal–oxide–semiconductor field effect transistors(MOSFETs) is investigated via simulation. The device is found to ... The synergistic effect of total ionizing dose(TID) and single event gate rupture(SEGR) in SiC power metal–oxide–semiconductor field effect transistors(MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer. 展开更多
关键词 SiC power MOSFET total ionizing dose(TID) single event gate rupture(SEGR) synergistic effect TCAD simulation
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Impact of switching frequencies on the TID response of SiC power MOSFETs 被引量:2
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作者 Sheng Yang Xiaowen Liang +9 位作者 Jiangwei Cui Qiwen Zheng Jing Sun Mohan Liu Dang Zhang Haonan Feng Xuefeng Yu Chuanfeng Xiang Yudong Li Qi Guo 《Journal of Semiconductors》 EI CAS CSCD 2021年第8期73-76,共4页
Different switching frequencies are required when SiC metal-oxide-semiconductor field-effect transistors(MOSFETs)are switching in a space environment.In this study,the total ionizing dose(TID)responses of SiC power MO... Different switching frequencies are required when SiC metal-oxide-semiconductor field-effect transistors(MOSFETs)are switching in a space environment.In this study,the total ionizing dose(TID)responses of SiC power MOSFETs are investigated under different switching frequencies from 1 kHz to 10 MHz.A significant shift was observed in the threshold voltage as the frequency increased,which resulted in premature failure of the drain-source breakdown voltage and drain-source leakage current.The degradation is attributed to the high activation and low recovery rates of traps at high frequencies.The results of this study suggest that a targeted TID irradiation test evaluation method can be developed according to the actual switching frequency of SiC power MOSFETs. 展开更多
关键词 SiC power MOSFET switching frequency oxide trap total ionizing dose TRANSISTOR semiconductor theory
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SEGR-and SEB-hardened structure with DSPSOI in power MOSFETs 被引量:2
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作者 Zhaohuan Tang Xinghua Fu +4 位作者 Fashun Yang Kaizhou Tan Kui Ma Xue Wu Jiexing Lin 《Journal of Semiconductors》 EI CAS CSCD 2017年第12期68-72,共5页
Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture(SEGR) and single event burnout(SEB), which will degrade the r... Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture(SEGR) and single event burnout(SEB), which will degrade the running safety and reliability of spacecraft, are the two typical failure modes in power MOSFETs. In this paper, based on recombination mechanism of interface between oxide and silicon, a novel hardened power MOSFETs structure for SEGR and SEB is proposed. The structure comprises double stagger partial silicon-on-insulator(DSPSOI) layers. Results show that the safety operation area(SOA) of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50% when the linear-energy-transfer value of heavy ion is a constant of 98 MeV·cm^2/mg in the whole incident track, and the other parameters are almost maintained at the same value. Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs. 展开更多
关键词 power mosfets partial silicon-on-insulator single event gate rupture single event burnout
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MUIS多脉冲雪崩应力下的器件退化特性
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作者 何荣华 《集成电路应用》 2021年第2期14-15,共2页
阐述Power MOSFET在多脉冲雪崩应力下的器件电参数退化和退化机制,提出了在半导体工艺制程中改善/延缓MUIS器件退化的方法,对国内集成电路尤其是汽车电子的应用具有参考意义。
关键词 power MOSFET 多脉冲UIS 器件退化 集成电路 汽车电子
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Power MOSFET UIS性能改善的研究
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作者 何荣华 《电子技术(上海)》 2020年第7期4-7,共4页
分析UIS失效的发生机理,提出了改善UIS性能的三个方面,避免产生极端电场强度、避免缺陷产生电流聚集效应、合适的沟槽深度保证charge balance电荷平衡。并且能够紧扣实验,通过实验结果来详细论证这三个观点。提出在半导体工艺制程和集... 分析UIS失效的发生机理,提出了改善UIS性能的三个方面,避免产生极端电场强度、避免缺陷产生电流聚集效应、合适的沟槽深度保证charge balance电荷平衡。并且能够紧扣实验,通过实验结果来详细论证这三个观点。提出在半导体工艺制程和集成电路器件设计过程中改善UIS能力与一致性的方法。 展开更多
关键词 集成电路 半导体器件 性能改善 power MOSFET Unclamped Inductive Switching
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