In the field of energy conversion,the increasing attention on power electronic equipment is fault detection and diagnosis.A power electronic circuit is an essential part of a power electronic system.The state of its i...In the field of energy conversion,the increasing attention on power electronic equipment is fault detection and diagnosis.A power electronic circuit is an essential part of a power electronic system.The state of its internal components affects the performance of the system.The stability and reliability of an energy system can be improved by studying the fault diagnosis of power electronic circuits.Therefore,an algorithm based on adaptive simulated annealing particle swarm optimization(ASAPSO)was used in the present study to optimize a backpropagation(BP)neural network employed for the online fault diagnosis of a power electronic circuit.We built a circuit simulation model in MATLAB to obtain its DC output voltage.Using Fourier analysis,we extracted fault features.These were normalized as training samples and input to an unoptimized BP neural network and BP neural networks optimized by particle swarm optimization(PSO)and the ASAPSO algorithm.The accuracy of fault diagnosis was compared for the three networks.The simulation results demonstrate that a BP neural network optimized with the ASAPSO algorithm has higher fault diagnosis accuracy,better reliability,and adaptability and can more effectively diagnose and locate faults in power electronic circuits.展开更多
The incidence chromatic number of G is the least number of colors such that G has an incidence coloring. It is proved that the incidence chromatic number of Cn^p, the p-th power of the circuit graph, is 2p ＋ 1 if and...The incidence chromatic number of G is the least number of colors such that G has an incidence coloring. It is proved that the incidence chromatic number of Cn^p, the p-th power of the circuit graph, is 2p ＋ 1 if and only if n = k（2p ＋ 1）, for other cases： its incidence chromatic number is at most 2p ＋ [r/k] ＋ 2, where n = k（p ＋ 1） ＋ r, k is a positive integer. This upper bound is tight for some cases.展开更多
The downlink energy-efficient transmission schedule with non-ideal circuit power over Wreless networks involving a single transmitter and multiple receivers was investigated. According to the special structure of the ...The downlink energy-efficient transmission schedule with non-ideal circuit power over Wreless networks involving a single transmitter and multiple receivers was investigated. According to the special structure of the problem, a novel algorithm called OOSCPMR （the optimal offine scheduling with non-ideal circuit power for multi-receivers） is proposed, and the optimal offine solutions to optimize the energy- efficient transmission policy are found. The packets to be transmitted can be divided into two types where one type of packet is determined to be transmitted using the enrgy- efficient tansmission time, and the other type of packet is determined by the ID moveright algorithm. Finally, an energy-efficient online schedule is developed based on te proposed OOSCPMR algoriAm. Simulation results show that the optima offline transmission schedule provides te lower bound performance for the online tansmission schedule. The proposed optimal offline and online policy is more energy efficient than the existing schemes tat assume ideal circuit power.展开更多
The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power...The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.展开更多
Based on the fundamental relationship among the circuit power, the circuit delay and the supply voltage, four theorems associated with the application of dynamic voltage scaling （DVS） policies are proposed and prove...Based on the fundamental relationship among the circuit power, the circuit delay and the supply voltage, four theorems associated with the application of dynamic voltage scaling （DVS） policies are proposed and proved. First, the existence characteristics of the optimal supply voltage for a single task are proved, which suggests that the optimal supply voltage for the single task should be selected only within a one-dimensional term, and the corresponding task end time by the optimal supply voltage should be identical with its deadline. Then, it is pointed out that the minimum energy consumption that the DVS policy can obtain when completing a single task is certainly lower than that of the dynamic power management （DPM） policy or the combined DVS＋DPM policy under the same conditions. Finally, the theorem of energy consumption minimization for a multi-task group is proposed, which declares that it is necessary to keep the processor in the execution state during the whole task period to obtain the minimum energy consumption, while satisfying the deadline constraints of any task.展开更多
Modeling and analysis of far field power extraction circuits for passive UHF RF identification （RFID） applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF v...Modeling and analysis of far field power extraction circuits for passive UHF RF identification （RFID） applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF voltage multiplier using Schottky diodes. To reduce the complexity of the proposed model, a simple linear approximation for Schottky diode is introduced. Measurement results show considerable agreement with the values calculated by the proposed model. With the derived model, optimization on stage number for voltage multiplier to achieve maximum power conversion efficiency is discussed. Furthermore, according to the Bode-Fano criterion and the proposed model, a limitation on maximum power up range for passive UHF RFID power extraction circuits is also studied.展开更多
A new configuration of a resonant full-bridge flying capacitor multicell inverter has been designed and constructed with the aim of achieving an extended output voltage frequency range with low harmonic distortion and...A new configuration of a resonant full-bridge flying capacitor multicell inverter has been designed and constructed with the aim of achieving an extended output voltage frequency range with low harmonic distortion and reduced semiconductor commutation losses. This configuration was tested as a power supply for two different coaxial dielectric barrier discharge reactors, one of them employed for electric characterization and the other one for inorganic compound elimination in an aqueous solution. Two different gas mixtures, 90% Ar-10% 02 and 80% Ar-20% 02, were individually supplied during the experiments; the results showed a high- efficiency removal of meta-cresol （m-cresol） to the order of 98%, which was obtained by adding more oxygen to the plasma gas mixture.展开更多
A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage l...A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method, With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-pm 1.8-V digital CMOS technology, consumes less power than previously reported designs.展开更多
This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory（EEPROM）.The low power is minimized by a capacitance divider circuit ...This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory（EEPROM）.The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique.The high efficiency is dependent on the zero threshold voltage（V_（th）） MOSFET and the charge transfer switch（CTS） charge pump.The proposed high voltage generator circuit has been implemented in a 0.35μm EEPROM CMOS process.Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48μW and a higher pumping efficiency（83.3%） than previously reported circuits.This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation.展开更多
This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier （LNA）, current-reuse V-I converter, active double balanced mixer and transimpedance amplifier for short range device...This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier （LNA）, current-reuse V-I converter, active double balanced mixer and transimpedance amplifier for short range device （SRD） applications. With the proposed current-reuse LNA, the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices. The RF front-end was fabricated in 0.18μm RFCMOS process and occupies a silicon area of just 0.11 mm^2. Operating in 433 MHz band, the measurement results show the RF front-end achieves a conversion gain of 29.7 dB, a double side band noise figure of 9.7 dB, an input referenced third intercept point of -24.9 dBm with only 1.44 mA power consumption from 1.8 V supply. Compared to other reported front-ends, it has an advantage in power consumption.展开更多
A reconfigurable multi-mode multi-band transceiver for low power short-range wireless communication applications is presented.Its low intermediate frequency(IF) receiver with 3 MHz IF carrier frequency and the direct-...A reconfigurable multi-mode multi-band transceiver for low power short-range wireless communication applications is presented.Its low intermediate frequency(IF) receiver with 3 MHz IF carrier frequency and the direct-conversion transmitter support reconfigurable signal bandwidths from 250 kHz to 2 MHz and support a highest data rate of 3 Mbps for MSK modulation.An integrated multi-band PLL frequency synthesizer is utilized to provide the quadrature LO signals from about 300 MHz to 1 GHz for the transceiver multi-band application. The transceiver has been implemented in a 0.18μm CMOS process.The measurement results at the maximum gain mode show that the receiver achieves a noise figure(NF) of 4.9/5.5 dB and an input 3rd order intermodulation point(IIP3) of-19.6/-18.2 dBm in 400/900 MHz band.The transmitter working in 400/900 MHz band can deliver 10.2/7.3 dBm power to a 50Ωload.The transceiver consumes 32.9/35.6 mW in receive mode and 47.4/50.1 mW in transmit mode in 400/900 MHz band,respectively.展开更多
Recently, triboelectric nanogenerators （TENGs）, as a collection technology with characteristics of high reliability, high energy density and low cost, has attracted more and more attention. However, the energy comin...Recently, triboelectric nanogenerators （TENGs）, as a collection technology with characteristics of high reliability, high energy density and low cost, has attracted more and more attention. However, the energy coming from TENGs needs to be stored in a storage unit effectively due to its unstable ac output. The traditional energy storage circuit has an extremely low energy storage efficiency for TENGs because of their high internal impedance. This paper presents a new power management circuit used to optimize the energy using efficiency of TENGs, and realize large load capacity. The power management circuit mainly includes rectification storage circuit and DC-DC management circuit. A rotating TENG with maximal energy output of 106 mW at 170 rpm based on PCB is used for the experimental verification. Experimental results show that the power energy transforming to the storage capacitor reach up to 53 mW and the energy using efficiency is calculated as 50%. When different loading resistances range from 0.82 to 34.5 k^2 are connected to the storage capacitor in parallel, the power energy stored in the storage capacitor is all about 52.5 mW. Getting through the circuit, the power energy coming from the TENGs can be used to drive numerous conventional electronics, such as wearable watches.展开更多
In the reversely switched dynistor(RSD)-based pulse power circuits,a magnetic switch is usually necessary to be applied together with a main switch.It occupies space and needs a magnetic reset.In this paper,a method o...In the reversely switched dynistor(RSD)-based pulse power circuits,a magnetic switch is usually necessary to be applied together with a main switch.It occupies space and needs a magnetic reset.In this paper,a method of designing a RSD-based pulse circuit without a magnetic switch is proposed.In the pulse circuit,a RBDT(reverse blocking diode thyristor)is used to separate the two capacitors and provide an energy branch.The pre-charge time of the RSD can be guaranteed by the energy conversion between the capacitors and inductors,instead of the saturation of the magnetic switch.In addition,the energy which is reused to trigger the RSD is based on an inductor.The pulse circuit is evaluated by simulations and practical experiments.According to the experimental results,the factors affecting the load pulse current and triggering of the RSD and RBDT are studied.Meanwhile,a method to reduce the current in the trigger switch,which is a potential problem in the pulse circuit,is proposed.展开更多
This paper presents a solution to the circulating current fault of aircraft power supply.The DC-link type Variable Frequency to Constant Frequency(VFCF)converter system is the preferred scheme to feed the constant 400...This paper presents a solution to the circulating current fault of aircraft power supply.The DC-link type Variable Frequency to Constant Frequency(VFCF)converter system is the preferred scheme to feed the constant 400 Hz load in an aircraft with a variable frequency power supply.Due to the requirement of aircraft standards,both grounds of the rectification and inversion stage are tied to the metal frame of the aircraft.With such a tied ground,the DC bus voltage rises greatly,and a large circulating current appears in the casing as the ground,which leads to equipment failure and potential safety hazards.According to the existing methods of circulating current fault suppression,this paper analyzes the causes of the above faults and the harmonic components of circulating current and points out the limitations of the existing methods.Therefore,a Common-Mode(CM)choke-based method is proposed to provide a high impedance in the path of the CM circulating current.By doing so,the circulating current can be suppressed without the additional burden of the hardware and control algorithm,which is quite friendly for quality control of mass-production aircraft.Moreover,a simplified mathematic model of the VFCF converter system is derived to calculate the minimum inductance value reference of the CM choke,which saves the weight of passive devices to the greatest extent.Finally,simulation and experimental results are studied to verify the effectiveness of the proposed method.展开更多
This paper presents a 6 kb SRAM that uses a novel 10T cell to achieve a minimum operating voltage of 320 mV in a 130 nm CMOS process. A number of low power circuit techniques are included to enable the proposed SRAM t...This paper presents a 6 kb SRAM that uses a novel 10T cell to achieve a minimum operating voltage of 320 mV in a 130 nm CMOS process. A number of low power circuit techniques are included to enable the proposed SRAM to operate in the subthreshold region. The reverse short channel effect and the reverse narrow channel effect are utilized to improve the performance of the SRAM. A novel subthreshold pulse generation circuit produces an ideal pulse to make read operation stable. A floating write bit-line effectively reduces the standby leakage consumption. Finally, a short read bit-line makes the read operation fast and energy-saving. Measurements indicate that these techniques are effective, the SRAM can operate at 800 kHz and consume 1.94/zW at its lowest voltage （320 mV）.展开更多
基金supported by the 2022 Project for Improving the Basic Research Ability of Young and Middle-aged Teachers in Guangxi Universities(Grant No.2022KY0209).
文摘In the field of energy conversion,the increasing attention on power electronic equipment is fault detection and diagnosis.A power electronic circuit is an essential part of a power electronic system.The state of its internal components affects the performance of the system.The stability and reliability of an energy system can be improved by studying the fault diagnosis of power electronic circuits.Therefore,an algorithm based on adaptive simulated annealing particle swarm optimization(ASAPSO)was used in the present study to optimize a backpropagation(BP)neural network employed for the online fault diagnosis of a power electronic circuit.We built a circuit simulation model in MATLAB to obtain its DC output voltage.Using Fourier analysis,we extracted fault features.These were normalized as training samples and input to an unoptimized BP neural network and BP neural networks optimized by particle swarm optimization(PSO)and the ASAPSO algorithm.The accuracy of fault diagnosis was compared for the three networks.The simulation results demonstrate that a BP neural network optimized with the ASAPSO algorithm has higher fault diagnosis accuracy,better reliability,and adaptability and can more effectively diagnose and locate faults in power electronic circuits.
基金Supported by NSFC(10201022,10571124,10726008)Supported by SRCPBMCE(KM200610028002)Supported by BNSF(1012003)
文摘The incidence chromatic number of G is the least number of colors such that G has an incidence coloring. It is proved that the incidence chromatic number of Cn^p, the p-th power of the circuit graph, is 2p ＋ 1 if and only if n = k（2p ＋ 1）, for other cases： its incidence chromatic number is at most 2p ＋ [r/k] ＋ 2, where n = k（p ＋ 1） ＋ r, k is a positive integer. This upper bound is tight for some cases.
基金The National Natural Science Foundation of China(No.61571123,61521061)the National Science and Technology Major Project(No.2016ZX03001011-005)+1 种基金the Research Fund of National Mobile Communications Research Laboratory of Southeast University(No.2017A03)Qing Lan Project
文摘The downlink energy-efficient transmission schedule with non-ideal circuit power over Wreless networks involving a single transmitter and multiple receivers was investigated. According to the special structure of the problem, a novel algorithm called OOSCPMR （the optimal offine scheduling with non-ideal circuit power for multi-receivers） is proposed, and the optimal offine solutions to optimize the energy- efficient transmission policy are found. The packets to be transmitted can be divided into two types where one type of packet is determined to be transmitted using the enrgy- efficient tansmission time, and the other type of packet is determined by the ID moveright algorithm. Finally, an energy-efficient online schedule is developed based on te proposed OOSCPMR algoriAm. Simulation results show that the optima offline transmission schedule provides te lower bound performance for the online tansmission schedule. The proposed optimal offline and online policy is more energy efficient than the existing schemes tat assume ideal circuit power.
基金supported in part by the National Natural Science Foundation of China(No.61306027)
文摘The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.
文摘Based on the fundamental relationship among the circuit power, the circuit delay and the supply voltage, four theorems associated with the application of dynamic voltage scaling （DVS） policies are proposed and proved. First, the existence characteristics of the optimal supply voltage for a single task are proved, which suggests that the optimal supply voltage for the single task should be selected only within a one-dimensional term, and the corresponding task end time by the optimal supply voltage should be identical with its deadline. Then, it is pointed out that the minimum energy consumption that the DVS policy can obtain when completing a single task is certainly lower than that of the dynamic power management （DPM） policy or the combined DVS＋DPM policy under the same conditions. Finally, the theorem of energy consumption minimization for a multi-task group is proposed, which declares that it is necessary to keep the processor in the execution state during the whole task period to obtain the minimum energy consumption, while satisfying the deadline constraints of any task.
基金supported by the High Technology Research and Development Program of Tianjin (No. 05YFGZGX02300)
文摘Modeling and analysis of far field power extraction circuits for passive UHF RF identification （RFID） applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF voltage multiplier using Schottky diodes. To reduce the complexity of the proposed model, a simple linear approximation for Schottky diode is introduced. Measurement results show considerable agreement with the values calculated by the proposed model. With the derived model, optimization on stage number for voltage multiplier to achieve maximum power conversion efficiency is discussed. Furthermore, according to the Bode-Fano criterion and the proposed model, a limitation on maximum power up range for passive UHF RFID power extraction circuits is also studied.
文摘A new configuration of a resonant full-bridge flying capacitor multicell inverter has been designed and constructed with the aim of achieving an extended output voltage frequency range with low harmonic distortion and reduced semiconductor commutation losses. This configuration was tested as a power supply for two different coaxial dielectric barrier discharge reactors, one of them employed for electric characterization and the other one for inorganic compound elimination in an aqueous solution. Two different gas mixtures, 90% Ar-10% 02 and 80% Ar-20% 02, were individually supplied during the experiments; the results showed a high- efficiency removal of meta-cresol （m-cresol） to the order of 98%, which was obtained by adding more oxygen to the plasma gas mixture.
基金the 973 Program of China (Grant No.G1999032903)the National Science Fund for Distinguished Young Scholars (Grant No.60025101)the Major Program of National Natural Science Foundation of China (Grant No.90707002)
文摘A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method, With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-pm 1.8-V digital CMOS technology, consumes less power than previously reported designs.
基金supported by the National Natural Science Foundation of China(No.61072010)
文摘This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory（EEPROM）.The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique.The high efficiency is dependent on the zero threshold voltage（V_（th）） MOSFET and the charge transfer switch（CTS） charge pump.The proposed high voltage generator circuit has been implemented in a 0.35μm EEPROM CMOS process.Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48μW and a higher pumping efficiency（83.3%） than previously reported circuits.This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation.
文摘This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier （LNA）, current-reuse V-I converter, active double balanced mixer and transimpedance amplifier for short range device （SRD） applications. With the proposed current-reuse LNA, the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices. The RF front-end was fabricated in 0.18μm RFCMOS process and occupies a silicon area of just 0.11 mm^2. Operating in 433 MHz band, the measurement results show the RF front-end achieves a conversion gain of 29.7 dB, a double side band noise figure of 9.7 dB, an input referenced third intercept point of -24.9 dBm with only 1.44 mA power consumption from 1.8 V supply. Compared to other reported front-ends, it has an advantage in power consumption.
基金supported by the National Natural Science Foundation of China(No.60806008)the National High Technology Research and Development Program of China(No.2008AA010708)
文摘A reconfigurable multi-mode multi-band transceiver for low power short-range wireless communication applications is presented.Its low intermediate frequency(IF) receiver with 3 MHz IF carrier frequency and the direct-conversion transmitter support reconfigurable signal bandwidths from 250 kHz to 2 MHz and support a highest data rate of 3 Mbps for MSK modulation.An integrated multi-band PLL frequency synthesizer is utilized to provide the quadrature LO signals from about 300 MHz to 1 GHz for the transceiver multi-band application. The transceiver has been implemented in a 0.18μm CMOS process.The measurement results at the maximum gain mode show that the receiver achieves a noise figure(NF) of 4.9/5.5 dB and an input 3rd order intermodulation point(IIP3) of-19.6/-18.2 dBm in 400/900 MHz band.The transmitter working in 400/900 MHz band can deliver 10.2/7.3 dBm power to a 50Ωload.The transceiver consumes 32.9/35.6 mW in receive mode and 47.4/50.1 mW in transmit mode in 400/900 MHz band,respectively.
文摘Recently, triboelectric nanogenerators （TENGs）, as a collection technology with characteristics of high reliability, high energy density and low cost, has attracted more and more attention. However, the energy coming from TENGs needs to be stored in a storage unit effectively due to its unstable ac output. The traditional energy storage circuit has an extremely low energy storage efficiency for TENGs because of their high internal impedance. This paper presents a new power management circuit used to optimize the energy using efficiency of TENGs, and realize large load capacity. The power management circuit mainly includes rectification storage circuit and DC-DC management circuit. A rotating TENG with maximal energy output of 106 mW at 170 rpm based on PCB is used for the experimental verification. Experimental results show that the power energy transforming to the storage capacitor reach up to 53 mW and the energy using efficiency is calculated as 50%. When different loading resistances range from 0.82 to 34.5 k^2 are connected to the storage capacitor in parallel, the power energy stored in the storage capacitor is all about 52.5 mW. Getting through the circuit, the power energy coming from the TENGs can be used to drive numerous conventional electronics, such as wearable watches.
基金This work was supported by the National Natural Science Foundation of China(51877092,51377069).
文摘In the reversely switched dynistor(RSD)-based pulse power circuits,a magnetic switch is usually necessary to be applied together with a main switch.It occupies space and needs a magnetic reset.In this paper,a method of designing a RSD-based pulse circuit without a magnetic switch is proposed.In the pulse circuit,a RBDT(reverse blocking diode thyristor)is used to separate the two capacitors and provide an energy branch.The pre-charge time of the RSD can be guaranteed by the energy conversion between the capacitors and inductors,instead of the saturation of the magnetic switch.In addition,the energy which is reused to trigger the RSD is based on an inductor.The pulse circuit is evaluated by simulations and practical experiments.According to the experimental results,the factors affecting the load pulse current and triggering of the RSD and RBDT are studied.Meanwhile,a method to reduce the current in the trigger switch,which is a potential problem in the pulse circuit,is proposed.
基金supported by the Natural Science Foundation for Young Scientists of Shanxi Province,China(No.52007154).
文摘This paper presents a solution to the circulating current fault of aircraft power supply.The DC-link type Variable Frequency to Constant Frequency(VFCF)converter system is the preferred scheme to feed the constant 400 Hz load in an aircraft with a variable frequency power supply.Due to the requirement of aircraft standards,both grounds of the rectification and inversion stage are tied to the metal frame of the aircraft.With such a tied ground,the DC bus voltage rises greatly,and a large circulating current appears in the casing as the ground,which leads to equipment failure and potential safety hazards.According to the existing methods of circulating current fault suppression,this paper analyzes the causes of the above faults and the harmonic components of circulating current and points out the limitations of the existing methods.Therefore,a Common-Mode(CM)choke-based method is proposed to provide a high impedance in the path of the CM circulating current.By doing so,the circulating current can be suppressed without the additional burden of the hardware and control algorithm,which is quite friendly for quality control of mass-production aircraft.Moreover,a simplified mathematic model of the VFCF converter system is derived to calculate the minimum inductance value reference of the CM choke,which saves the weight of passive devices to the greatest extent.Finally,simulation and experimental results are studied to verify the effectiveness of the proposed method.
基金Project supported by the National Natural Science Foundation of China(No.61306039)the Next Generation of Information Technology for Sensing China(No.XDA06020401)
文摘This paper presents a 6 kb SRAM that uses a novel 10T cell to achieve a minimum operating voltage of 320 mV in a 130 nm CMOS process. A number of low power circuit techniques are included to enable the proposed SRAM to operate in the subthreshold region. The reverse short channel effect and the reverse narrow channel effect are utilized to improve the performance of the SRAM. A novel subthreshold pulse generation circuit produces an ideal pulse to make read operation stable. A floating write bit-line effectively reduces the standby leakage consumption. Finally, a short read bit-line makes the read operation fast and energy-saving. Measurements indicate that these techniques are effective, the SRAM can operate at 800 kHz and consume 1.94/zW at its lowest voltage （320 mV）.
