A power MOSFET with integrated split gate and dummy gate(SD-MOS) is proposed and demonstrated by the TCAD SENTAURUS.The split gate is surrounded by the source and shielded by the dummy gate.Consequently,the coupling a...A power MOSFET with integrated split gate and dummy gate(SD-MOS) is proposed and demonstrated by the TCAD SENTAURUS.The split gate is surrounded by the source and shielded by the dummy gate.Consequently,the coupling area between the split gate and the drain electrode is reduced,thus the gate-to-drain charge(Q_(GD)),reverse transfer capacitance(C_(RSS)) and turn-off loss(E_(off)) are significantly decreased.Moreover,the MOS-channel diode is controlled by the dummy gate with ultra-thin gate oxide t_(ox),which can be turned on before the parasitic P-base/N-drift diode at the reverse conduction,then the majority carriers are injected to the N-drift to attenuate the minority injection.Therefore,the reverse recovery charge(Q_(RR)),time(T_(RR)) and peak current(I_(RRM)) are effectively reduced at the reverse freewheeling state.Additionally,the specific on-resistance(R_(on,sp)) and breakdown voltage(BV) are also studied to evaluate the static properties of the proposed SD-MOS.The simulation results show that the Q_(GD) of 6 nC/cm^(2),the C_(RSS) of 1.1 pF/cm^(2) at the V_(DS) of 150 V,the QRR of 1.2 μC/cm^(2) and the R_(on,sp) of 8.4 mΩ·cm^(2) are obtained,thus the figures of merit(FOM) including Q_(GD) ×R_(on,sp) of50 nC·mΩ,E_(off) × R_(on,sp) of 0.59 mJ·mΩ and the Q_(RR) × R_(on,sp) of 10.1 μC·mΩ are achieved for the proposed SD-MOS.展开更多
In nuclear fusion power supply systems, the thyristors often need to be connected in parallel for sustaining large current. However, research on the reverse recovery transient of parallel thyristors has not been repor...In nuclear fusion power supply systems, the thyristors often need to be connected in parallel for sustaining large current. However, research on the reverse recovery transient of parallel thyristors has not been reported yet. When several thyristors are connected in parallel,they cannot turn-off at the same moment, and thus the turn-off model based on a single thyristor is no longer suitable. In this paper, an analysis is presented for the reverse recovery transient of parallel thyristors. Parallel thyristors can be assumed as one virtual thyristor so that the reverse recovery current can be modeled by an exponential function. Through equivalent transformation of the rectifier circuit, the commutating over-voltage can be calculated based on Kirchhoff’s equation. The reverse recovery current and commutation over-voltage waveforms are measured on an experiment platform for a high power rectifier supply. From the measurement results, it is concluded that the modeling method is acceptable.展开更多
A new SiC superjunction power MOSFET device using high-k insulator and p-type pillar with an integrated Schottky barrier diode(Hk-SJ-SBD MOSFET)is proposed,and has been compared with the SiC high-k MOSFET(Hk MOSFET),S...A new SiC superjunction power MOSFET device using high-k insulator and p-type pillar with an integrated Schottky barrier diode(Hk-SJ-SBD MOSFET)is proposed,and has been compared with the SiC high-k MOSFET(Hk MOSFET),SiC superjuction MOSFET(SJ MOSFET)and the conventional SiC MOSFET in this article.In the proposed SiC Hk-SJ-SBD MOSFET,under the combined action of the p-type region and the Hk dielectric layer in the drift region,the concentration of the N-drift region and the current spreading layer can be increased to achieve an ultra-low specific on-resistance(Ron,sp).The integrated Schottky barrier diode(SBD)also greatly improves the reverse recovery performance of the device.TCAD simulation results indicate that the Ron,sp of the proposed SiC Hk-SJ-SBD MOSFET is 0.67 mΩ·cm^(2)with a 2240 V breakdown voltage(BV),which is more than 72.4%,23%,5.6%lower than that of the conventional SiC MOSFET,Hk SiC MOSFET and SJ SiC MOSFET with the 1950,2220,and 2220V BV,respectively.The reverse recovery time and reverse recovery charge of the proposed MOSFET is 16 ns and18 nC,which are greatly reduced by more than 74%and 94%in comparison with those of all the conventional SiC MOSFET,Hk SiC MOSFET and SJ SiC MOSFET,due to the integrated SBD in the proposed MOSFET.And the trade-off relationship between the Ron,sp and the BV is also significantly improved compared with that of the conventional MOSFET,Hk MOSFET and SJ MOSFET as well as the MOSFETs in other previous literature,respectively.In addition,compared with conventional SJ SiC MOSFET,the proposed SiC MOSFET has better immunity to charge imbalance,which may bring great application prospects.展开更多
A novel SiC double-trench metal-oxide-semiconductor field effect transistor(MOSFET) with integrated MOS-channel diode is proposed and investigated by Sentaurus TCAD simulation. The new SiC MOSFET has a trench gate and...A novel SiC double-trench metal-oxide-semiconductor field effect transistor(MOSFET) with integrated MOS-channel diode is proposed and investigated by Sentaurus TCAD simulation. The new SiC MOSFET has a trench gate and a stepped-trench source, and features an integrated MOS-channel diode on the top sidewall of the source trench(MT MOS). In the reverse conduction state, the MOS-channel diode turns on firstly to prevent the internal parasitic body diode being activated, and thus reduces the turn-on voltage VFand suppresses the bipolar degradation phenomena. The VFof1.70 V(@Ids=-100 A/cm^(2)) for the SiC MT MOS is 38.2% lower than that of SiC double-trench MOSFET(DT MOS).Meanwhile, the reverse recovery charge Qrrof the MT MOS is 58.7% lower than that of the DT MOS at Iload= 700 A/cm^(2),and thus the reverse recovery loss is reduced. Furthermore, owing to the modulation effect induced by the double trenches,the MT MOS preserves the same superior forward conduction and blocking performance as those of DT MOS, with 22.9% and 18.2% improvement on breakdown voltage and RON,spcompared to the trench gate MOSFET with planar integrated SBD(ST MOS).展开更多
A novel 4H-SiC trench MOSFET is presented and investigated by simulation in this paper.The device features an integrated Schottky barrier diode and an L-shaped P^+shielding region beneath the gate trench and aside one...A novel 4H-SiC trench MOSFET is presented and investigated by simulation in this paper.The device features an integrated Schottky barrier diode and an L-shaped P^+shielding region beneath the gate trench and aside one wall of the gate trench(S-TMOS).The integrated Schottky barrier diode works as a free-wheeling diode in reverse recovery and reverse conduction,which significantly reduces reverse recovery charge(Q_(rr))and reverse turn-on voltage(VF).The L-shaped P^+region effectively shields the coupling of gate and drain,resulting in a lower gate–drain capacitance(C_(gd))and date–drain charge(Q_(gd)).Compared with that of conventional SiC trench MOSFET(C-TMOS),the V_F and Q_(rr)of S-TMOS has reduced by 44%and 75%,respectively,with almost the same forward output current and reverse breakdown voltage.Moreover,the S-TMOS reduces Q_(gd)and C_(gd)by 32%and 22%,respectively,in comparison with C-TMOS.展开更多
A novel planar vertical double-diffused metal-oxide-semiconductor （VDMOS） structure with an ultra-low specific on-resistance （Ron,sp）, whose distinctive feature is the use of inhomogeneous floating p-islands in th...A novel planar vertical double-diffused metal-oxide-semiconductor （VDMOS） structure with an ultra-low specific on-resistance （Ron,sp）, whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region, is proposed. The theoretical limit of its Ron,sp is deduced, the influence of structure parameters on the breakdown voltage （BV） and Ron,sp are investigated, and the optimized results with BV of 83 V and Ron,sp of 54 mΩ.mm2 are obtained. Simulations show that the inhomogeneous-floating-islands metal-oxide-semiconductor field-effect transistor （MOSFET） has a superior ＂Ron,sp/BV＂ trade-off to the conventional VDMOS （a 38% reduction of Ron,sp with the same BV） and the homogeneous-floating-islands MOSFET （a 10% reduction of Ron,sp with the same BV）. The inhomogeneous-floatingislands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET. Its reverse recovery peak current, reverse recovery time and reverse recovery charge are about 50, 80 and 40% of those of the superjunction MOSFET, respectively.展开更多
An accumulation gate enhanced power U-shaped metal-oxide-semiconductor field-effect-transistor（UMOSFET） integrated with a Schottky rectifier is proposed.In this device,a Schottky rectifier is integrated into each ce...An accumulation gate enhanced power U-shaped metal-oxide-semiconductor field-effect-transistor（UMOSFET） integrated with a Schottky rectifier is proposed.In this device,a Schottky rectifier is integrated into each cell of the accumulation gate enhanced power UMOSFET.Specific on-resistances of 7.7 m.mm 2 and 6.5 m.mm 2 for the gate bias voltages of 5 V and 10 V are achieved,respectively,and the breakdown voltage is 61 V.The numerical simulation shows a 25% reduction in the reverse recovery time and about three orders of magnitude reduction in the leakage current as compared with the accumulation gate enhanced power UMOSFET.展开更多
An accumulation gate enhanced power U-shaped metal-oxide-semiconductor field-effect-transistor(UMOSFET) integrated with a Schottky rectifier is proposed.In this device,a Schottky rectifier is integrated into each cell...An accumulation gate enhanced power U-shaped metal-oxide-semiconductor field-effect-transistor(UMOSFET) integrated with a Schottky rectifier is proposed.In this device,a Schottky rectifier is integrated into each cell of the accumulation gate enhanced power UMOSFET.Specific on-resistances of 7.7 m.mm 2 and 6.5 m.mm 2 for the gate bias voltages of 5 V and 10 V are achieved,respectively,and the breakdown voltage is 61 V.The numerical simulation shows a 25% reduction in the reverse recovery time and about three orders of magnitude reduction in the leakage current as compared with the accumulation gate enhanced power UMOSFET.展开更多
Using p~＋-type crystalline Si with n~＋-type nanocrystalline Si（nc-Si） and n~＋-type crystalline Si with p~＋-type nc-Si mosaic structures as electrodes,a type of power diode was prepared with epitaxial technique a...Using p~＋-type crystalline Si with n~＋-type nanocrystalline Si（nc-Si） and n~＋-type crystalline Si with p~＋-type nc-Si mosaic structures as electrodes,a type of power diode was prepared with epitaxial technique and plasmaenhanced chemical vapor deposition（PECVD） method.Firstly,the basic p~＋-n^--n~＋-type Si diode was fabricated by epitaxially growing p~＋- and n~＋-type layers on two sides of a lightly doped n^--type Si wafer respectively.Secondly,heavily phosphorus-doped Si film was deposited with PECVD on the lithography mask etched p~＋-type Si side of the basic device to form a component with mosaic anode.Thirdly,heavily boron-doped Si film was deposited on the etched n~＋-type Si side of the second device to form a diode with mosaic anode and mosaic cathode.The images of high resolution transmission electronic microscope and patterns of X-ray diffraction reveal nanocrystallization in the phosphorus- and boron-deposited films.Electrical measurements such as capacitancevoltage relation,current-voltage feature and reverse recovery waveform were carried out to clarify the performance of prepared devices.The important roles of（n^-）Si/（p~＋）nc-Si and（n^-）Si/（n~＋）nc-Si junctions in the static and dynamic conduction processes in operating diodes were investigated.The performance of mosaic devices was compared to that of a basic one.展开更多
基金Project supported by the National Natural Science Foundation of China (Grants No. 61604027 and 61704016)the Chongqing Natural Science Foundation, China (Grant No. cstc2020jcyj-msxmX0550)。
文摘A power MOSFET with integrated split gate and dummy gate(SD-MOS) is proposed and demonstrated by the TCAD SENTAURUS.The split gate is surrounded by the source and shielded by the dummy gate.Consequently,the coupling area between the split gate and the drain electrode is reduced,thus the gate-to-drain charge(Q_(GD)),reverse transfer capacitance(C_(RSS)) and turn-off loss(E_(off)) are significantly decreased.Moreover,the MOS-channel diode is controlled by the dummy gate with ultra-thin gate oxide t_(ox),which can be turned on before the parasitic P-base/N-drift diode at the reverse conduction,then the majority carriers are injected to the N-drift to attenuate the minority injection.Therefore,the reverse recovery charge(Q_(RR)),time(T_(RR)) and peak current(I_(RRM)) are effectively reduced at the reverse freewheeling state.Additionally,the specific on-resistance(R_(on,sp)) and breakdown voltage(BV) are also studied to evaluate the static properties of the proposed SD-MOS.The simulation results show that the Q_(GD) of 6 nC/cm^(2),the C_(RSS) of 1.1 pF/cm^(2) at the V_(DS) of 150 V,the QRR of 1.2 μC/cm^(2) and the R_(on,sp) of 8.4 mΩ·cm^(2) are obtained,thus the figures of merit(FOM) including Q_(GD) ×R_(on,sp) of50 nC·mΩ,E_(off) × R_(on,sp) of 0.59 mJ·mΩ and the Q_(RR) × R_(on,sp) of 10.1 μC·mΩ are achieved for the proposed SD-MOS.
基金supported by the International Thermonuclear Experimental Reactor Project of China(No.2008 GB104000)
文摘In nuclear fusion power supply systems, the thyristors often need to be connected in parallel for sustaining large current. However, research on the reverse recovery transient of parallel thyristors has not been reported yet. When several thyristors are connected in parallel,they cannot turn-off at the same moment, and thus the turn-off model based on a single thyristor is no longer suitable. In this paper, an analysis is presented for the reverse recovery transient of parallel thyristors. Parallel thyristors can be assumed as one virtual thyristor so that the reverse recovery current can be modeled by an exponential function. Through equivalent transformation of the rectifier circuit, the commutating over-voltage can be calculated based on Kirchhoff’s equation. The reverse recovery current and commutation over-voltage waveforms are measured on an experiment platform for a high power rectifier supply. From the measurement results, it is concluded that the modeling method is acceptable.
基金supported in part by the National Natural Science Foundation of China(Grant No.61974015)Key R&D Project of Science and Technology Plan of the Sichuan province(Grant No.2021YFG0139)the Open Foundation of State Key Laboratory of Electronic Thin Films and Integrated Devices of China(Grant No.KFJJ201806)。
文摘A new SiC superjunction power MOSFET device using high-k insulator and p-type pillar with an integrated Schottky barrier diode(Hk-SJ-SBD MOSFET)is proposed,and has been compared with the SiC high-k MOSFET(Hk MOSFET),SiC superjuction MOSFET(SJ MOSFET)and the conventional SiC MOSFET in this article.In the proposed SiC Hk-SJ-SBD MOSFET,under the combined action of the p-type region and the Hk dielectric layer in the drift region,the concentration of the N-drift region and the current spreading layer can be increased to achieve an ultra-low specific on-resistance(Ron,sp).The integrated Schottky barrier diode(SBD)also greatly improves the reverse recovery performance of the device.TCAD simulation results indicate that the Ron,sp of the proposed SiC Hk-SJ-SBD MOSFET is 0.67 mΩ·cm^(2)with a 2240 V breakdown voltage(BV),which is more than 72.4%,23%,5.6%lower than that of the conventional SiC MOSFET,Hk SiC MOSFET and SJ SiC MOSFET with the 1950,2220,and 2220V BV,respectively.The reverse recovery time and reverse recovery charge of the proposed MOSFET is 16 ns and18 nC,which are greatly reduced by more than 74%and 94%in comparison with those of all the conventional SiC MOSFET,Hk SiC MOSFET and SJ SiC MOSFET,due to the integrated SBD in the proposed MOSFET.And the trade-off relationship between the Ron,sp and the BV is also significantly improved compared with that of the conventional MOSFET,Hk MOSFET and SJ MOSFET as well as the MOSFETs in other previous literature,respectively.In addition,compared with conventional SJ SiC MOSFET,the proposed SiC MOSFET has better immunity to charge imbalance,which may bring great application prospects.
基金the support by the Science & Technology Program (High voltage and high power SiC material, devices and the application demonstration in power electronic transformers) of the State Grid Corporation of China Co. Ltd.supported by the National Key Research and Development Program of China (Grant No. 2016YFB0400502)。
文摘A novel SiC double-trench metal-oxide-semiconductor field effect transistor(MOSFET) with integrated MOS-channel diode is proposed and investigated by Sentaurus TCAD simulation. The new SiC MOSFET has a trench gate and a stepped-trench source, and features an integrated MOS-channel diode on the top sidewall of the source trench(MT MOS). In the reverse conduction state, the MOS-channel diode turns on firstly to prevent the internal parasitic body diode being activated, and thus reduces the turn-on voltage VFand suppresses the bipolar degradation phenomena. The VFof1.70 V(@Ids=-100 A/cm^(2)) for the SiC MT MOS is 38.2% lower than that of SiC double-trench MOSFET(DT MOS).Meanwhile, the reverse recovery charge Qrrof the MT MOS is 58.7% lower than that of the DT MOS at Iload= 700 A/cm^(2),and thus the reverse recovery loss is reduced. Furthermore, owing to the modulation effect induced by the double trenches,the MT MOS preserves the same superior forward conduction and blocking performance as those of DT MOS, with 22.9% and 18.2% improvement on breakdown voltage and RON,spcompared to the trench gate MOSFET with planar integrated SBD(ST MOS).
基金supported by the National Key Research and Development Program of China(No.2016YFB0400502)。
文摘A novel 4H-SiC trench MOSFET is presented and investigated by simulation in this paper.The device features an integrated Schottky barrier diode and an L-shaped P^+shielding region beneath the gate trench and aside one wall of the gate trench(S-TMOS).The integrated Schottky barrier diode works as a free-wheeling diode in reverse recovery and reverse conduction,which significantly reduces reverse recovery charge(Q_(rr))and reverse turn-on voltage(VF).The L-shaped P^+region effectively shields the coupling of gate and drain,resulting in a lower gate–drain capacitance(C_(gd))and date–drain charge(Q_(gd)).Compared with that of conventional SiC trench MOSFET(C-TMOS),the V_F and Q_(rr)of S-TMOS has reduced by 44%and 75%,respectively,with almost the same forward output current and reverse breakdown voltage.Moreover,the S-TMOS reduces Q_(gd)and C_(gd)by 32%and 22%,respectively,in comparison with C-TMOS.
基金Project supported by the National Key Scientific and Technological Project (Grant No. 2011ZX02503-005)the Fundamental Research Funds for the Central Universities (Grant No. ZYGX2010J038)
文摘A novel planar vertical double-diffused metal-oxide-semiconductor （VDMOS） structure with an ultra-low specific on-resistance （Ron,sp）, whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region, is proposed. The theoretical limit of its Ron,sp is deduced, the influence of structure parameters on the breakdown voltage （BV） and Ron,sp are investigated, and the optimized results with BV of 83 V and Ron,sp of 54 mΩ.mm2 are obtained. Simulations show that the inhomogeneous-floating-islands metal-oxide-semiconductor field-effect transistor （MOSFET） has a superior ＂Ron,sp/BV＂ trade-off to the conventional VDMOS （a 38% reduction of Ron,sp with the same BV） and the homogeneous-floating-islands MOSFET （a 10% reduction of Ron,sp with the same BV）. The inhomogeneous-floatingislands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET. Its reverse recovery peak current, reverse recovery time and reverse recovery charge are about 50, 80 and 40% of those of the superjunction MOSFET, respectively.
基金Project supported by the National Natural Science Foundation of China （Grant No. 60906048） the Program for New Century Excellent Talents in University China （Grant No. NCET-10-0052）
文摘An accumulation gate enhanced power U-shaped metal-oxide-semiconductor field-effect-transistor（UMOSFET） integrated with a Schottky rectifier is proposed.In this device,a Schottky rectifier is integrated into each cell of the accumulation gate enhanced power UMOSFET.Specific on-resistances of 7.7 m.mm 2 and 6.5 m.mm 2 for the gate bias voltages of 5 V and 10 V are achieved,respectively,and the breakdown voltage is 61 V.The numerical simulation shows a 25% reduction in the reverse recovery time and about three orders of magnitude reduction in the leakage current as compared with the accumulation gate enhanced power UMOSFET.
基金Project supported by the National Natural Science Foundation of China (Grant No. 60906048)the Program for New Century Excellent Talents in University,China (Grant No. NCET-10-0052)
文摘An accumulation gate enhanced power U-shaped metal-oxide-semiconductor field-effect-transistor(UMOSFET) integrated with a Schottky rectifier is proposed.In this device,a Schottky rectifier is integrated into each cell of the accumulation gate enhanced power UMOSFET.Specific on-resistances of 7.7 m.mm 2 and 6.5 m.mm 2 for the gate bias voltages of 5 V and 10 V are achieved,respectively,and the breakdown voltage is 61 V.The numerical simulation shows a 25% reduction in the reverse recovery time and about three orders of magnitude reduction in the leakage current as compared with the accumulation gate enhanced power UMOSFET.
基金supported by the National Natural Science Foundation of China(No.61274006)
文摘Using p~＋-type crystalline Si with n~＋-type nanocrystalline Si（nc-Si） and n~＋-type crystalline Si with p~＋-type nc-Si mosaic structures as electrodes,a type of power diode was prepared with epitaxial technique and plasmaenhanced chemical vapor deposition（PECVD） method.Firstly,the basic p~＋-n^--n~＋-type Si diode was fabricated by epitaxially growing p~＋- and n~＋-type layers on two sides of a lightly doped n^--type Si wafer respectively.Secondly,heavily phosphorus-doped Si film was deposited with PECVD on the lithography mask etched p~＋-type Si side of the basic device to form a component with mosaic anode.Thirdly,heavily boron-doped Si film was deposited on the etched n~＋-type Si side of the second device to form a diode with mosaic anode and mosaic cathode.The images of high resolution transmission electronic microscope and patterns of X-ray diffraction reveal nanocrystallization in the phosphorus- and boron-deposited films.Electrical measurements such as capacitancevoltage relation,current-voltage feature and reverse recovery waveform were carried out to clarify the performance of prepared devices.The important roles of（n^-）Si/（p~＋）nc-Si and（n^-）Si/（n~＋）nc-Si junctions in the static and dynamic conduction processes in operating diodes were investigated.The performance of mosaic devices was compared to that of a basic one.
