The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are un...The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are unified into a single one,which is compressed by the extended coding technique.A reconfigurable scan test application mechanism is presented,in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added.The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks,and to an ITC' 02 benchmark circuit.Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores,the proposed scheme can not only improve test data compression/decompression,but also reduce the redundant shift and capture cycles during scan testing,decreasing SoC test application time effectively.展开更多
The test vector compression is a keytechnique to reduce IC test time and cost since theexplosion of the test data of system on chip (SoC) inrecent years. To reduce the bandwidth requirementbetween the automatic test e...The test vector compression is a keytechnique to reduce IC test time and cost since theexplosion of the test data of system on chip (SoC) inrecent years. To reduce the bandwidth requirementbetween the automatic test equipment (ATE) and theCUT (circuit under test) effectively, a novel VSPTIDR(variable shifting prefix-tail identifier reverse) code fortest stimulus data compression is designed. Theencoding scheme is defined and analyzed in detail, andthe decoder is presented and discussed. While theprobability of 0 bits in the test set is greater than 0.92,the compression ratio from VSPTIDR code is betterthan the frequency-directed run-length (FDR) code,which can be proved by theoretical analysis andexperiments. And the on-chip area overhead ofVSPTIDR decoder is about 15.75 % less than the FDRdecoder.展开更多
基金Supported by the National Natural Science Fund of China (No.60876028)the key Project of Natural Science Foundation of the Anhui Higher Education Institutions (No.KJ2010A280)
文摘The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are unified into a single one,which is compressed by the extended coding technique.A reconfigurable scan test application mechanism is presented,in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added.The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks,and to an ITC' 02 benchmark circuit.Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores,the proposed scheme can not only improve test data compression/decompression,but also reduce the redundant shift and capture cycles during scan testing,decreasing SoC test application time effectively.
基金supported by the Shenzhen Government R&D Project under Grant No.JC200903160361A
文摘The test vector compression is a keytechnique to reduce IC test time and cost since theexplosion of the test data of system on chip (SoC) inrecent years. To reduce the bandwidth requirementbetween the automatic test equipment (ATE) and theCUT (circuit under test) effectively, a novel VSPTIDR(variable shifting prefix-tail identifier reverse) code fortest stimulus data compression is designed. Theencoding scheme is defined and analyzed in detail, andthe decoder is presented and discussed. While theprobability of 0 bits in the test set is greater than 0.92,the compression ratio from VSPTIDR code is betterthan the frequency-directed run-length (FDR) code,which can be proved by theoretical analysis andexperiments. And the on-chip area overhead ofVSPTIDR decoder is about 15.75 % less than the FDRdecoder.
基金Acknowledgements The supports provided for the paper by the National Natural Science Foundation of China （Grant No. 50778019） and the Natural Science Foundation of Beijing （Grant No. 8092024） are gratefully appreciated.
