An analytical model of gate-all-around （GAA） silicon nanowire tunneling field effect transistors （NW-TFETs） is developted based on the surface potential solutions in the channel direction and considering the band ...An analytical model of gate-all-around （GAA） silicon nanowire tunneling field effect transistors （NW-TFETs） is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling （BTBT） efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kane＇s expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results.展开更多
Tunneling field effect transistors（TFETs） based on two-dimensional materials are promising contenders to the traditional metal oxide semiconductor field effect transistor, mainly due to potential applications in low...Tunneling field effect transistors（TFETs） based on two-dimensional materials are promising contenders to the traditional metal oxide semiconductor field effect transistor, mainly due to potential applications in low power devices. Here,we investigate the TFETs based on two different integration types： in-plane and vertical heterostructures composed of two kinds of layered phosphorous（β-P and δ-P） by ab initio quantum transport simulations. NDR effects have been observed in both in-plane and vertical heterostructures, and the effects become significant with the highest peak-to-valley ratio（PVR）when the intrinsic region length is near zero. Compared with the in-plane TFET based on β-P and δ-P, better performance with a higher on/off current ratio of - 10-6 and a steeper subthreshold swing（SS） of - 23 mV/dec is achieved in the vertical TFET. Such differences in the NDR effects, on/off current ratio and SS are attributed to the distinct interaction nature of theβ-P and δ-P layers in the in-plane and vertical heterostructures.展开更多
Nanowires with gate-all-around(GAA) structures are widely considered as the most promising candidate for 3-nm technology with the best ability of suppressing the short channel effects,and tunneling field effect transi...Nanowires with gate-all-around(GAA) structures are widely considered as the most promising candidate for 3-nm technology with the best ability of suppressing the short channel effects,and tunneling field effect transistors(TFETs)based on GAA structures also present improved performance.In this paper,a non-quasi-static(NQS) device model is developed for nanowire GAA TFETs.The model can predict the transient current and capacitance varying with operation frequency,which is beyond the ability of the quasi-static(QS) model published before.Excellent agreements between the model results and numerical simulations are obtained.Moreover,the NQS model is derived from the published QS model including the current-voltage(I-V) and capacitance-voltage(C-V) characteristics.Therefore,the NQS model is compatible with the QS model for giving comprehensive understanding of GAA TFETs and would be helpful for further study of TFET circuits based on nanowire GAA structure.展开更多
Subthreshold characteristics of vertical tunneling field effect transistors（VTFETs） with an nC-pocket in the pC-source are studied by simulating the transfer characteristics with a commercial device simulator.Three ...Subthreshold characteristics of vertical tunneling field effect transistors（VTFETs） with an nC-pocket in the pC-source are studied by simulating the transfer characteristics with a commercial device simulator.Three types of subthreshold characteristics are demonstrated for the device with different pocket thicknesses and doping concentrations.Band diagram analysis shows that such a VTFET can be treated as a gate-controlled tunnel diode connected in series with a conventional n-channel metal-oxide-semiconductor FET.This VTFET can work either as a TFET or an n-MOSFET in the subthreshold region,depending on the turn-on sequence of these two components.To our knowledge,this is the first time such a device model has been used to explain the subthreshold characteristics of this kind of VTFET and the simulation results demonstrate that such a device model is convictive and valid.Our results indicate that the design of the nC pocket is crucial for such a VTFET in order to achieve ultra-steep turn-on characteristics.展开更多
A dielectric modulation strategy for gate oxide material that enhances the sensing performance of biosensors in junction-less vertical tunnel field effect transistors(TFETs)is reported.The junction-less technique,in w...A dielectric modulation strategy for gate oxide material that enhances the sensing performance of biosensors in junction-less vertical tunnel field effect transistors(TFETs)is reported.The junction-less technique,in which metals with specific work functions are deposited on the source region to modulate the channel conductivity,is used to provide the necessary doping for the proper functioning of the device.TCAD simulation studies of the proposed structure and junction structure have been compared,and showed an enhanced rectification of 10^(4) times.The proposed structure is designed to have a nanocavity of length 10 nm on the left-and right-hand sides of the fixed gate dielectric,which improves the biosensor capture area,and hence the sensitivity.By considering neutral and charged biomolecules with different dielectric constants,TCAD simulation studies were compared for their sensitivities.The off-state current IOFFcan be used as a suitable sensing parameter because it has been observed that the proposed sensor exhibits a significant variation in drain current.Additionally,it has been investigated how positively and negatively charged biomolecules affect the drain current and threshold voltage.To explore the device performance when the nanogaps are fully filled,half filled and unevenly filled,extensive TCAD simulations have been run.The proposed TFET structure is further benchmarked to other structures to show its better sensing capabilities.展开更多
The fundamental advantages of carbon-based graphene material,such as its high tunnelling probability,symmetric band structure(linear dependence of the energy band on the wave direction),low effective mass,and characte...The fundamental advantages of carbon-based graphene material,such as its high tunnelling probability,symmetric band structure(linear dependence of the energy band on the wave direction),low effective mass,and characteristics of its 2D atomic layers,are the main focus of this research work.The impact of channel thickness,gate under-lap,asymmetric source/drain doping method,workfunction of gate contact,and High-K material on Graphene-based Tunnel Field Effect Transistor(TFET)is analyzed with 20 nm technology.Physical modelling and electrical characteristic performance have been simulated using the Atlas device simulator of SILVACO TCAD with user-defined material syntax for the newly included graphene material in comparison to silicon carbide(SiC).The simulation results in significant suppression of ambipolar current to voltage characteristics of TFET and modelled device exhibits a significant improvement in subthreshold swing(0.0159 V/decade),the ratio of Ion/Ioff(1000),and threshold voltage(-0.2 V with highly doped p-type source and 0.2 V with highly doped n-type drain)with power supply of 0.5 V,which make it useful for low power digital applications.展开更多
The tunneling current in a graphene nanoribbon tunnel field effect transistor(GNR-TFET) has been quantum mechanically modeled. The tunneling current in the GNR-TFET was compared based on calculations of the Dirac-like...The tunneling current in a graphene nanoribbon tunnel field effect transistor(GNR-TFET) has been quantum mechanically modeled. The tunneling current in the GNR-TFET was compared based on calculations of the Dirac-like equation and Schrodinger’s equation. To calculate the electron transmittance, a numerical approach-namely the transfer matrix method(TMM)-was employed and the Launder formula was used to compute the tunneling current. The results suggest that the tunneling currents that were calculated using both equations have similar characteristics for the same parameters, even though they have different values. The tunneling currents that were calculated by applying the Dirac-like equation were lower than those calculated using Schrodinger’s equation.展开更多
In this work, a double-gate-all-around tunneling field-effect transistor is proposed. The performance of the novel device is studied by numerical simulation. The results show that with a thinner body and an additional...In this work, a double-gate-all-around tunneling field-effect transistor is proposed. The performance of the novel device is studied by numerical simulation. The results show that with a thinner body and an additional core gate, the novel device achieves a steeper subthreshold slope, less susceptibility to the short channel effect, higher on-state current, and larger on/off current ratio than the traditional gate-all-around tunneling field-effect transistor. The excellent performance makes the proposed structure more attractive to further dimension scaling.展开更多
The tunnel field-effect transistor (TFET) is proposed by using the advantages of dopingless and line-tunneling technology. The line tunneling is created due to the fact that the gate electric field is aligned with the...The tunnel field-effect transistor (TFET) is proposed by using the advantages of dopingless and line-tunneling technology. The line tunneling is created due to the fact that the gate electric field is aligned with the tunneling direction, which dramatically enhances tunneling area and tunneling current. Moreover, the effects of the structure parameters such as the length between top gate and source electrode, the length between top gate and drain electrode, the distance between bottom gate and drain electrode, and the metal position on the on-state current, electric field and energy band are investigated and optimized. In addition, analog/radio-frequency performance and linearity characteristics are studied. All results demonstrate that the proposed device not only enhances the on/of current ratio and reduces the subthreshold swing, but also offers eight times improvement in cut-off frequency and gain band product as compared with the conventional point tunneling dopingless TFET, at the same time;it shows better linearity and small distortions. This proposed device greatly enhances the potential of applications in dopingless TFET.展开更多
Theπ-πstacking is a well-recognized intermolecular interaction that is responsible for the construction of electron hopping channels in numerous conducting frameworks/aggregates.However,the exact role ofπ-to-πchan...Theπ-πstacking is a well-recognized intermolecular interaction that is responsible for the construction of electron hopping channels in numerous conducting frameworks/aggregates.However,the exact role ofπ-to-πchannels within typical single crystalline organic semiconductors remains unclear as the orientations of these molecules are diverse,and their control usually requires additional side chain groups that misrepresent the intrinsic properties of the original semiconducting molecules.Therefore,the construction of conduction channels with intrinsicπ-πstacking in the molecule-based device is crucial for the utilization of their unique transport characteristics and understanding of the transport mechanism.To this end,we present a molecular intercalation strategy that integrates two-dimensional layered materials with functional organic semiconductor molecules for functional molecule-based electronics.Various organic semiconductor molecules can be effectively intercalated into the van der Waals gaps of semi-metallic TaS_(2) withπ-πstacking configuration and controlled intercalant content.Our results show that the vertical charge transport in the stacking direction shows a tunneling-dominated mechanism that strongly depends on the molecular structures.Furthermore,we demonstrated a new type of molecule-based vertical transistor in which TaS_(2) andπ-πstacked organic molecules function as the electrical contact and the active channel,respectively.On/off ratios as high as 447 are achieved under electrostatic modulation in ionic liquid,comparable to the current state-of-the-art molecular transistors.Our study provides an ideal platform for probing intrinsic charge transport acrossπ-πstacked conjugated molecules and also a feasible approach for the construction of high-performance molecule-based electronic devices.展开更多
Dual-metal gate and gate–drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET).The effects of gate work function and gate–drain underlap leng...Dual-metal gate and gate–drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET).The effects of gate work function and gate–drain underlap length on the DC characteristics and analog/RF performance of CSP-TFET devices,such as the on-state current(I_(on)),ambipolar current(I_(amb)),transconductance(g_(m)),cut-off frequency(f_(T))and gain–bandwidth product(GBP),are analyzed and compared in this work.Also,a combination of both the dual-metal gate and gate–drain underlap designs has been proposed for the C-shaped pocket dual metal underlap TFET(CSP-DMUN-TFET),which contains a C-shaped pocket area that significantly increases the on-state current of the device;this combination design substantially reduces the ambipolar current.The results show that the CSP-DMUN-TFET demonstrates an excellent performance,including high I_(on)(9.03×10^(-4)A/μm),high I_(on)/I_(off)(~10^(11)),low SS_(avg)(~13 mV/dec),and low I_(amb)(2.15×10^(-17)A/μm).The CSP-DMUN-TFET has the capability to fully suppress ambipolar currents while maintaining high on-state currents,making it a potential replacement in the next generation of semiconductor devices.展开更多
For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel fi...For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel field effect transistor （DG-TFET） counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET.展开更多
We present a GaSb/In As junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the p...We present a GaSb/In As junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology.Numerical simulations resulted in an IOFF of 8×10^-17A/ m, ION of 9 A/ m, ION/IOFF of 1×10^11,subthreshold slope of 9.33 m V/dec and DIBL of 87 m V/V for GaSb/InAs JLTFET at a temperature of 300 K,gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.4 V.展开更多
A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poi...A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane＇s model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.展开更多
We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs （having low leakage）...We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs （having low leakage） are improved by junctionless TFETs through blending advantages of Junctionless FETs （with high on current）. We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in Iovv of - 9 × 10-16A/um, IoN of ,-20uA/um, ION/IoFF of--2× 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.展开更多
We propose a dynamic threshold voltage j unctionless tunnel FET （DT-JLTFET） in wnlcn me mresnolu voltage can be dynamically adjusted, resulting in higher ON-current. Through 2D numerical simulations, it is presented...We propose a dynamic threshold voltage j unctionless tunnel FET （DT-JLTFET） in wnlcn me mresnolu voltage can be dynamically adjusted, resulting in higher ON-current. Through 2D numerical simulations, it is presented that the threshold voltage in the DT-JLTFET can be adjusted by applying a voltage to the adjust gate. The impact of the threshold voltage shift on the overall performance of the device is also studied. A comparison is made between the dynamic threshold voltage characteristics of a silicon JLTFET and a Sio.7Geo.3 source JLTFET.展开更多
We have investigated the 20 nm p-type double gate junctionless tunnel field effect transistor （P-DGJLTFET） and the impact of variation of different device parameters on the performance parameters of the P-DGJLTFET i...We have investigated the 20 nm p-type double gate junctionless tunnel field effect transistor （P-DGJLTFET） and the impact of variation of different device parameters on the performance parameters of the P-DGJLTFET is discussed. We achieved excellent results of different performance parameters by taking the optimized device parameters of the P-DGJLTFET. Together with a high-k dielectric material （TiO2） of 20 nm gate length, the simulation results of the P-DGJLTFET show excellent characteristics with a high IoN of ～ 0.3 mA/μm, a low/OFF of ～ 30 fA/μm, a high ION/IOFF ratio of ～ 1×10^10, a subthreshold slope （SS） point of ～ 23 mV/decade, and an average SS of ～ 49 mV/decade at a supply voltage of -1 V and at room temperature, which indicates that PDGJLTFET is a promising candidate for sub-22 nm technology nodes in the implementation of integrated circuits.展开更多
A C-shaped pocket tunnel field effect transistor(CSP-TFET)has been designed and optimized based on the traditional double-gate TFETs by introducing a C-shaped pocket region between the source and channel to improve th...A C-shaped pocket tunnel field effect transistor(CSP-TFET)has been designed and optimized based on the traditional double-gate TFETs by introducing a C-shaped pocket region between the source and channel to improve the device performance.A gate-to-pocket overlapping structure is also examined in the proposed CSP-TFET to enhance the gate controllability.The effects of the pocket length,pocket doping concentration and gate-to-pocket overlapping structure on the DC and analog/RF characteristics of the CSP-TFET are estimated after calibrating the tunneling model in double-gate TFETs.The DC and analog/RF performance such as on-state current(Ion),on/off current ratio(Ion/Ioff),subthreshold swing(SS)transconductance(g;),cut-off frequency(f_(T))and gain-bandwidth product(GBP)are investigated.The optimized CSPTFET device exhibits excellent performance with high I_(off)(9.98×10^(-4)A/μm),high I_(on)/I_(off)(~10^(11)),as well as low SS(~12 m V/dec).The results reveal that the CSP-TFET device could be a potential alternative for the next generation of semiconductor devices.展开更多
A single gate Ⅲ-Ⅴ junctionless tunnel field effect transistor（SG-JLTFET） has been reported which shows excellent dc characteristics at low power supply operation.This device has a thin uniformly n-type doped chann...A single gate Ⅲ-Ⅴ junctionless tunnel field effect transistor（SG-JLTFET） has been reported which shows excellent dc characteristics at low power supply operation.This device has a thin uniformly n-type doped channel of GaSb i.e.gallium antimonide which is grown epitaxially over silicon substrate.The DC performance parameters such as I（on）,I（on）/I（off）,average and point subthreshold slope as well as device parameters for analog applications viz.transconductance gm,transconductance generation efficiency gm/ID,various capacitances and the unity gain frequency fT are studied using a device simulator.Along with examining its endurance to short channel effects,the performances are also compared with a Silicon Dual Gate Junctionless Tunnel FET（DG-JLTFET）.The DC and small signal analog performance reflects that GaSb SG-JLTFET has immense purview for extreme high-frequency and low-power applications.展开更多
A two-dimensional analytical model of double-gate（DG） tunneling field-effect transistors（TFETs） with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potentia...A two-dimensional analytical model of double-gate（DG） tunneling field-effect transistors（TFETs） with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile,the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate,and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.展开更多
基金supported by the National Natural Science Foundation of China(Grant Nos.61274096,61204043,61306042,61306045,and 61306132)the Guangdong Natural Science Foundation,China(Grant Nos.S2012010010533 and S2013040016878)+2 种基金the Shenzhen Science&Technology Foundation,China(Grant No.ZDSY20120618161735041)the Fundamental Research Project of the Shenzhen Science&Technology Foundation,China(Grant Nos.JCYJ20120618162600041,JCYJ20120618162526384,JCYJ20130402164725025,and JCYJ20120618162946025)the International Collaboration Project of the Shenzhen Science&Technology Foundation,China(Grant Nos.GJHZ20120618162120759,GJHZ20130417170946221,GJHZ20130417170908049,and GJHZ20120615142829482)
文摘An analytical model of gate-all-around （GAA） silicon nanowire tunneling field effect transistors （NW-TFETs） is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling （BTBT） efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kane＇s expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.11604019,61574020,and 61376018)the Ministry of Science and Technology of China(Grant No.2016YFA0301300)+1 种基金the Fund of State Key Laboratory of Information Photonics and Optical Communications(Beijing University of Posts and Telecommunications),Chinathe Fundamental Research Funds for the Central Universities,China(Grant No.2016RCGD22)
文摘Tunneling field effect transistors（TFETs） based on two-dimensional materials are promising contenders to the traditional metal oxide semiconductor field effect transistor, mainly due to potential applications in low power devices. Here,we investigate the TFETs based on two different integration types： in-plane and vertical heterostructures composed of two kinds of layered phosphorous（β-P and δ-P） by ab initio quantum transport simulations. NDR effects have been observed in both in-plane and vertical heterostructures, and the effects become significant with the highest peak-to-valley ratio（PVR）when the intrinsic region length is near zero. Compared with the in-plane TFET based on β-P and δ-P, better performance with a higher on/off current ratio of - 10-6 and a steeper subthreshold swing（SS） of - 23 mV/dec is achieved in the vertical TFET. Such differences in the NDR effects, on/off current ratio and SS are attributed to the distinct interaction nature of theβ-P and δ-P layers in the in-plane and vertical heterostructures.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 62004119 and 62201332)the Applied Basic Research Plan of Shanxi Province, China (Grant Nos. 20210302124647 and 20210302124028)。
文摘Nanowires with gate-all-around(GAA) structures are widely considered as the most promising candidate for 3-nm technology with the best ability of suppressing the short channel effects,and tunneling field effect transistors(TFETs)based on GAA structures also present improved performance.In this paper,a non-quasi-static(NQS) device model is developed for nanowire GAA TFETs.The model can predict the transient current and capacitance varying with operation frequency,which is beyond the ability of the quasi-static(QS) model published before.Excellent agreements between the model results and numerical simulations are obtained.Moreover,the NQS model is derived from the published QS model including the current-voltage(I-V) and capacitance-voltage(C-V) characteristics.Therefore,the NQS model is compatible with the QS model for giving comprehensive understanding of GAA TFETs and would be helpful for further study of TFET circuits based on nanowire GAA structure.
基金Project supported by the International Research Training Group
文摘Subthreshold characteristics of vertical tunneling field effect transistors（VTFETs） with an nC-pocket in the pC-source are studied by simulating the transfer characteristics with a commercial device simulator.Three types of subthreshold characteristics are demonstrated for the device with different pocket thicknesses and doping concentrations.Band diagram analysis shows that such a VTFET can be treated as a gate-controlled tunnel diode connected in series with a conventional n-channel metal-oxide-semiconductor FET.This VTFET can work either as a TFET or an n-MOSFET in the subthreshold region,depending on the turn-on sequence of these two components.To our knowledge,this is the first time such a device model has been used to explain the subthreshold characteristics of this kind of VTFET and the simulation results demonstrate that such a device model is convictive and valid.Our results indicate that the design of the nC pocket is crucial for such a VTFET in order to achieve ultra-steep turn-on characteristics.
文摘A dielectric modulation strategy for gate oxide material that enhances the sensing performance of biosensors in junction-less vertical tunnel field effect transistors(TFETs)is reported.The junction-less technique,in which metals with specific work functions are deposited on the source region to modulate the channel conductivity,is used to provide the necessary doping for the proper functioning of the device.TCAD simulation studies of the proposed structure and junction structure have been compared,and showed an enhanced rectification of 10^(4) times.The proposed structure is designed to have a nanocavity of length 10 nm on the left-and right-hand sides of the fixed gate dielectric,which improves the biosensor capture area,and hence the sensitivity.By considering neutral and charged biomolecules with different dielectric constants,TCAD simulation studies were compared for their sensitivities.The off-state current IOFFcan be used as a suitable sensing parameter because it has been observed that the proposed sensor exhibits a significant variation in drain current.Additionally,it has been investigated how positively and negatively charged biomolecules affect the drain current and threshold voltage.To explore the device performance when the nanogaps are fully filled,half filled and unevenly filled,extensive TCAD simulations have been run.The proposed TFET structure is further benchmarked to other structures to show its better sensing capabilities.
文摘The fundamental advantages of carbon-based graphene material,such as its high tunnelling probability,symmetric band structure(linear dependence of the energy band on the wave direction),low effective mass,and characteristics of its 2D atomic layers,are the main focus of this research work.The impact of channel thickness,gate under-lap,asymmetric source/drain doping method,workfunction of gate contact,and High-K material on Graphene-based Tunnel Field Effect Transistor(TFET)is analyzed with 20 nm technology.Physical modelling and electrical characteristic performance have been simulated using the Atlas device simulator of SILVACO TCAD with user-defined material syntax for the newly included graphene material in comparison to silicon carbide(SiC).The simulation results in significant suppression of ambipolar current to voltage characteristics of TFET and modelled device exhibits a significant improvement in subthreshold swing(0.0159 V/decade),the ratio of Ion/Ioff(1000),and threshold voltage(-0.2 V with highly doped p-type source and 0.2 V with highly doped n-type drain)with power supply of 0.5 V,which make it useful for low power digital applications.
基金supported by Hibah Penelitian Berbasi Kompetensi 2018 RISTEKDIKTI Republic of Indonesia
文摘The tunneling current in a graphene nanoribbon tunnel field effect transistor(GNR-TFET) has been quantum mechanically modeled. The tunneling current in the GNR-TFET was compared based on calculations of the Dirac-like equation and Schrodinger’s equation. To calculate the electron transmittance, a numerical approach-namely the transfer matrix method(TMM)-was employed and the Launder formula was used to compute the tunneling current. The results suggest that the tunneling currents that were calculated using both equations have similar characteristics for the same parameters, even though they have different values. The tunneling currents that were calculated by applying the Dirac-like equation were lower than those calculated using Schrodinger’s equation.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61176038 and 61474093)the Science and Technology Planning Project of Guangdong Province,China(Grant No.2015A010103002)the Technology Development Program of Shanxi Province,China(Grant No.2016GY075)
文摘In this work, a double-gate-all-around tunneling field-effect transistor is proposed. The performance of the novel device is studied by numerical simulation. The results show that with a thinner body and an additional core gate, the novel device achieves a steeper subthreshold slope, less susceptibility to the short channel effect, higher on-state current, and larger on/off current ratio than the traditional gate-all-around tunneling field-effect transistor. The excellent performance makes the proposed structure more attractive to further dimension scaling.
基金Project supported by the Natural Science Research Key Project of Universities of Anhui Province,China(Grant No.KJ2017A502)the Introduced Talent Project of Anhui Science and Technology University,China(Grant No.DQYJ201603)the Excellent Talents Supported Project of Colleges and Universities,China(Grant No.gxyq2018048)。
文摘The tunnel field-effect transistor (TFET) is proposed by using the advantages of dopingless and line-tunneling technology. The line tunneling is created due to the fact that the gate electric field is aligned with the tunneling direction, which dramatically enhances tunneling area and tunneling current. Moreover, the effects of the structure parameters such as the length between top gate and source electrode, the length between top gate and drain electrode, the distance between bottom gate and drain electrode, and the metal position on the on-state current, electric field and energy band are investigated and optimized. In addition, analog/radio-frequency performance and linearity characteristics are studied. All results demonstrate that the proposed device not only enhances the on/of current ratio and reduces the subthreshold swing, but also offers eight times improvement in cut-off frequency and gain band product as compared with the conventional point tunneling dopingless TFET, at the same time;it shows better linearity and small distortions. This proposed device greatly enhances the potential of applications in dopingless TFET.
基金support by the National Natural Science Foundation of China(Nos.22172075,92156024)the Fundamental Research Funds for the Central Universities in China(Nos.0210/14380174,14380273)+4 种基金Beijing National Laboratory for Molecular Sciences(No.BNLMS202107)Thousand Talents Plan of Jiangxi Province(No.jxsq2019102002)support by the National Natural Science Foundation of China(No.22033004)support from Early Career Scheme Project(No.21302821)General Research Fund Project(No.11314322)from the University Grants Committee of Hong Kong.
文摘Theπ-πstacking is a well-recognized intermolecular interaction that is responsible for the construction of electron hopping channels in numerous conducting frameworks/aggregates.However,the exact role ofπ-to-πchannels within typical single crystalline organic semiconductors remains unclear as the orientations of these molecules are diverse,and their control usually requires additional side chain groups that misrepresent the intrinsic properties of the original semiconducting molecules.Therefore,the construction of conduction channels with intrinsicπ-πstacking in the molecule-based device is crucial for the utilization of their unique transport characteristics and understanding of the transport mechanism.To this end,we present a molecular intercalation strategy that integrates two-dimensional layered materials with functional organic semiconductor molecules for functional molecule-based electronics.Various organic semiconductor molecules can be effectively intercalated into the van der Waals gaps of semi-metallic TaS_(2) withπ-πstacking configuration and controlled intercalant content.Our results show that the vertical charge transport in the stacking direction shows a tunneling-dominated mechanism that strongly depends on the molecular structures.Furthermore,we demonstrated a new type of molecule-based vertical transistor in which TaS_(2) andπ-πstacked organic molecules function as the electrical contact and the active channel,respectively.On/off ratios as high as 447 are achieved under electrostatic modulation in ionic liquid,comparable to the current state-of-the-art molecular transistors.Our study provides an ideal platform for probing intrinsic charge transport acrossπ-πstacked conjugated molecules and also a feasible approach for the construction of high-performance molecule-based electronic devices.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.52177185 and 62174055)。
文摘Dual-metal gate and gate–drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET).The effects of gate work function and gate–drain underlap length on the DC characteristics and analog/RF performance of CSP-TFET devices,such as the on-state current(I_(on)),ambipolar current(I_(amb)),transconductance(g_(m)),cut-off frequency(f_(T))and gain–bandwidth product(GBP),are analyzed and compared in this work.Also,a combination of both the dual-metal gate and gate–drain underlap designs has been proposed for the C-shaped pocket dual metal underlap TFET(CSP-DMUN-TFET),which contains a C-shaped pocket area that significantly increases the on-state current of the device;this combination design substantially reduces the ambipolar current.The results show that the CSP-DMUN-TFET demonstrates an excellent performance,including high I_(on)(9.03×10^(-4)A/μm),high I_(on)/I_(off)(~10^(11)),low SS_(avg)(~13 mV/dec),and low I_(amb)(2.15×10^(-17)A/μm).The CSP-DMUN-TFET has the capability to fully suppress ambipolar currents while maintaining high on-state currents,making it a potential replacement in the next generation of semiconductor devices.
文摘For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel field effect transistor （DG-TFET） counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET.
文摘We present a GaSb/In As junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology.Numerical simulations resulted in an IOFF of 8×10^-17A/ m, ION of 9 A/ m, ION/IOFF of 1×10^11,subthreshold slope of 9.33 m V/dec and DIBL of 87 m V/V for GaSb/InAs JLTFET at a temperature of 300 K,gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.4 V.
基金Project supported by the National Natural Science Foundation of China(No.61376106)the Graduate Innovation Fund of Anhui University
文摘A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane＇s model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.
文摘We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs （having low leakage） are improved by junctionless TFETs through blending advantages of Junctionless FETs （with high on current）. We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in Iovv of - 9 × 10-16A/um, IoN of ,-20uA/um, ION/IoFF of--2× 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.
文摘We propose a dynamic threshold voltage j unctionless tunnel FET （DT-JLTFET） in wnlcn me mresnolu voltage can be dynamically adjusted, resulting in higher ON-current. Through 2D numerical simulations, it is presented that the threshold voltage in the DT-JLTFET can be adjusted by applying a voltage to the adjust gate. The impact of the threshold voltage shift on the overall performance of the device is also studied. A comparison is made between the dynamic threshold voltage characteristics of a silicon JLTFET and a Sio.7Geo.3 source JLTFET.
文摘We have investigated the 20 nm p-type double gate junctionless tunnel field effect transistor （P-DGJLTFET） and the impact of variation of different device parameters on the performance parameters of the P-DGJLTFET is discussed. We achieved excellent results of different performance parameters by taking the optimized device parameters of the P-DGJLTFET. Together with a high-k dielectric material （TiO2） of 20 nm gate length, the simulation results of the P-DGJLTFET show excellent characteristics with a high IoN of ～ 0.3 mA/μm, a low/OFF of ～ 30 fA/μm, a high ION/IOFF ratio of ～ 1×10^10, a subthreshold slope （SS） point of ～ 23 mV/decade, and an average SS of ～ 49 mV/decade at a supply voltage of -1 V and at room temperature, which indicates that PDGJLTFET is a promising candidate for sub-22 nm technology nodes in the implementation of integrated circuits.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.52177185 and 62174055)Open Fund of Shanghai Key Laboratory of Multidimensional Information Processing,East China Normal University(Grant No.2019MIP002)。
文摘A C-shaped pocket tunnel field effect transistor(CSP-TFET)has been designed and optimized based on the traditional double-gate TFETs by introducing a C-shaped pocket region between the source and channel to improve the device performance.A gate-to-pocket overlapping structure is also examined in the proposed CSP-TFET to enhance the gate controllability.The effects of the pocket length,pocket doping concentration and gate-to-pocket overlapping structure on the DC and analog/RF characteristics of the CSP-TFET are estimated after calibrating the tunneling model in double-gate TFETs.The DC and analog/RF performance such as on-state current(Ion),on/off current ratio(Ion/Ioff),subthreshold swing(SS)transconductance(g;),cut-off frequency(f_(T))and gain-bandwidth product(GBP)are investigated.The optimized CSPTFET device exhibits excellent performance with high I_(off)(9.98×10^(-4)A/μm),high I_(on)/I_(off)(~10^(11)),as well as low SS(~12 m V/dec).The results reveal that the CSP-TFET device could be a potential alternative for the next generation of semiconductor devices.
文摘A single gate Ⅲ-Ⅴ junctionless tunnel field effect transistor（SG-JLTFET） has been reported which shows excellent dc characteristics at low power supply operation.This device has a thin uniformly n-type doped channel of GaSb i.e.gallium antimonide which is grown epitaxially over silicon substrate.The DC performance parameters such as I（on）,I（on）/I（off）,average and point subthreshold slope as well as device parameters for analog applications viz.transconductance gm,transconductance generation efficiency gm/ID,various capacitances and the unity gain frequency fT are studied using a device simulator.Along with examining its endurance to short channel effects,the performances are also compared with a Silicon Dual Gate Junctionless Tunnel FET（DG-JLTFET）.The DC and small signal analog performance reflects that GaSb SG-JLTFET has immense purview for extreme high-frequency and low-power applications.
基金Project supported by the National Natural Science Foundation of China(No.61376106)the University Natural Science Research Key Project of Anhui Province(No.KJ2016A169)the Introduced Talents Project of Anhui Science and Technology University
文摘A two-dimensional analytical model of double-gate（DG） tunneling field-effect transistors（TFETs） with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile,the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate,and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.
