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A New Clock-Driven ECO Placement Algorithm Based on Table-Lookup Delay Model
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作者 刘毅 洪先龙 +2 位作者 蔡懿慈 吴为民 Chung-Wen Albert Tsao 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2002年第5期473-478,共6页
A new clock-driven ECO placement algorithm is pr es ented for standard-cell layout design based on the table-lookup delay model.It considers useful clock skew information in the placement stage.It also modifies the ... A new clock-driven ECO placement algorithm is pr es ented for standard-cell layout design based on the table-lookup delay model.It considers useful clock skew information in the placement stage.It also modifies the positions of cells locally to make better preparation for the clock routing . Experimental results show that with little influence to other circuit performa nce,the algorithm can improve permissible skew range distribution evidently. 展开更多
关键词 CLOCK-DRIVEN incremental placement useful skew permissibl e skew range
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