Hemiparesis is one of the most common consequences of stroke. Advanced rehabilitation techniques are essential for restoring motor function in hemiplegic patients. Functional electrical stimulation applied to the affe...Hemiparesis is one of the most common consequences of stroke. Advanced rehabilitation techniques are essential for restoring motor function in hemiplegic patients. Functional electrical stimulation applied to the affected limb based on myoelectric signal from the unaffected limb is a promising therapy for hemiplegia. In this study, we developed a prototype system for evaluating this novel functional electrical stimulation-control strategy. Based on surface electromyography and a vector machine model, a self-administered, muki-movement, force-modulation functional electrical stimulation-prototype system for hemiplegia was implemented. This paper discusses the hardware design, the algorithm of the system, and key points of the self-oscillation-prone system. The experimental results demonstrate the feasibility of the prototype system for further clinical trials, which is being conducted to evaluate the efficacy of the proposed rehabilitation technique.展开更多
The paper presents a fully integrated ultra-wide band(UWB)low noise amplifier(LNA)for 3-10 GHz applications.It employs self-biased resistive-feedback and current-reused technique to achieve wide input matching and low...The paper presents a fully integrated ultra-wide band(UWB)low noise amplifier(LNA)for 3-10 GHz applications.It employs self-biased resistive-feedback and current-reused technique to achieve wide input matching and low power characteristics.An improved biased architecture is adopted in the second stage to attain a better gain-compensation performance.The design is verified with TSMC standard 1 P6 M 0.18μm RF CMOS process.The measurement results show that the parasitic problem of the transistors at high frequencies is solved.A high and flat S21 of 9.7±1.5 dB and the lowest NF 3.5 dB are achieved in the desired frequency band.The power consumption is only 7.5 mA under 1.6 V supply.The proposed LNA achieves broadband flat gain,low noise,and high linearity performance simultaneously,allowing it to be used in 3-10 GHz UWB applications.展开更多
To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural networks （ANN） hardware implementation methods, a bit-stream ANN construction method based on direct sigma-delta （Z-A...To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural networks （ANN） hardware implementation methods, a bit-stream ANN construction method based on direct sigma-delta （Z-A） signal processing is presented. The bit-stream adder, multiplier and fully digital X-A modulator used in the bit-stream linear ANN are implemented in a field programmable gate array （FPGA）. A bit-stream linear ANN based on these bit-stream modules is presented and implemented. To verify the function and performance of the bit-stream linear ANN, the bit-stream adaptive predictor and the bit-stream adaptive noise cancellation system are presented. The predicted result of the bit-stream adaptive predictor is very close to the desired signal. Also, the bit-stream adaptive noise cancellation system removes the electric power noise effectively.展开更多
A 12-Gbit/s low-power,wide-bandwidh CMOS(complementary metal oxide semiconductor)dual negative feedback feed-forward common gate(DNFFCG)differential trans-impedance amplifier(TIA)is presented for the veryshort-reach(V...A 12-Gbit/s low-power,wide-bandwidh CMOS(complementary metal oxide semiconductor)dual negative feedback feed-forward common gate(DNFFCG)differential trans-impedance amplifier(TIA)is presented for the veryshort-reach(VSR)optoelectronic integrated circuit(OEIC)receiver.The dominant pole of the input node is shifted up to a high frequency,and thus the bandwidth of the CMOS DNFFCG TIA is improved.Besides,two negative feedback loops are used to reduce the input impedance and further increase the bandwidth.The proposed TIA was fabricated using TSMC 0.18 jxm CMOS technology.The whole circuit has a compact chip area,the core area of which is only 0.003 6 mm2.The power consumption is 14.6 mW excluding 2-stage differential buffers.The test results indicate that the 3 dB bandwidth of 9 GHz is achieved with a 1 8 V supply voltage and its trans-impedance gain is 49.2 dBH.The measured average equivalent input noise current density is 28.1 pA H z12.Under the same process conditions,the DNFFCG has better gain bandwidth product compared with those in the published papers.展开更多
Voluntary participation of hemiplegic patients is crucial for functional electrical stimulation therapy.A wearable functional electrical stimulation system has been proposed for real-time volitional hand motor functio...Voluntary participation of hemiplegic patients is crucial for functional electrical stimulation therapy.A wearable functional electrical stimulation system has been proposed for real-time volitional hand motor function control using the electromyography bridge method.Through a series of novel design concepts,including the integration of a detecting circuit and an analog-to-digital converter,a miniaturized functional electrical stimulation circuit technique,a low-power super-regeneration chip for wireless receiving,and two wearable armbands,a prototype system has been established with reduced size,power,and overall cost.Based on wrist joint torque reproduction and classification experiments performed on six healthy subjects,the optimized surface electromyography thresholds and trained logistic regression classifier parameters were statistically chosen to establish wrist and hand motion control with high accuracy.Test results showed that wrist flexion/extension,hand grasp,and finger extension could be reproduced with high accuracy and low latency.This system can build a bridge of information transmission between healthy limbs and paralyzed limbs,effectively improve voluntary participation of hemiplegic patients,and elevate efficiency of rehabilitation training.展开更多
A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circui...A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circuit, is adopted to reduce the frequency division step. The NF-DSM, which can obtain smooth output spectra, is proposed to generate the fractional part of the division ratio, moreover, the integer part of the division ratio is realized by a divider-by-2/3 circuit chain. Fabricated in TSMC 0.18 μm RF CMOS technology, the fractional frequency divider achieves a measured operation frequency from 0.5 GHz to 8 GHz. With a 1.8 V supply voltage, the maximum current consumption of the whole divider is 17.5 mA, and the chip area is 0.58 mm^2, including the pads.展开更多
A fully integrated wideband voltage-controlled-oscillator(VCO) based on current-reused topology is presented. The overall scheme contains two sub-VCOs, which are controlled by a switch to cover a wide output frequency...A fully integrated wideband voltage-controlled-oscillator(VCO) based on current-reused topology is presented. The overall scheme contains two sub-VCOs, which are controlled by a switch to cover a wide output frequency range. Fabricated in TSMC 65 nm CMOS technology, the measured output frequency of the VCO ranges from 3.991 GHz to 9.713 GHz,achieving a tuning range of 83.5%. And the worst and best phase noise at 1 MHz offset are-93.09 dBc/Hz and-111.97 dBc/Hz, respectively. With a 1.2 V supply voltage, the VCO core consumes a current of 3.7-5.1 mA across the entire frequency range. The chip area is 0.51 mm^2, including the pads. Moreover, the proposed VCO provides a figure-of-merit-with-tuning-range(FOM_T) of-191 dBc/Hz to-197 dBc/Hz.展开更多
Epidural stimulation of the spinal cord is a promising technique for the recovery of motor function after spinal cord injury.The key challenges within the reconstruction of motor function for paralyzed limbs are the p...Epidural stimulation of the spinal cord is a promising technique for the recovery of motor function after spinal cord injury.The key challenges within the reconstruction of motor function for paralyzed limbs are the precise control of sites and parameters of stimulation.To activate lower-limb muscles precisely by epidural spinal cord stimulation,we proposed a high-density,flexible electrode array.We determined the regions of motor function that were activated upon epidural stimulation of the spinal cord in a rat model with complete spinal cord,which was established by a transection method.For evaluating the effect of stimulation,the evoked potentials were recorded from bilateral lowerlimb muscles,including the vastus lateralis,semitendinosus,tibialis anterior,and medial gastrocnemius.To determine the appropriate stimulation sites and parameters of the lower muscles,the stimulation characteristics were studied within the regions in which motor function was activated upon spinal cord stimulation.In the vastus lateralis and medial gastrocnemius,these regions were symmetrically located at the lateral site of L1 and the medial site of L2 vertebrae segment,respectively.The tibialis anterior and semitendinosus only responded to stimulation simultaneously with other muscles.The minimum and maximum stimulation threshold currents of the vastus lateralis were higher than those of the medial gastrocnemius.Our results demonstrate the ability to identify specific stimulation sites of lower muscles using a high-density and flexible array.They also provide a reference for selecting the appropriate conditions for implantable stimulation for animal models of spinal cord injury.This study was approved by the Animal Research Committee of Southeast University,China(approval No.20190720001) on July 20,2019.展开更多
A 4th-order low-pass filter （LPF） based on active-Gm-RC structure for multi-standard system application is presented in this paper. The performances of LPF are controlled by a 1-bit control- voltage, and the cut-off...A 4th-order low-pass filter （LPF） based on active-Gm-RC structure for multi-standard system application is presented in this paper. The performances of LPF are controlled by a 1-bit control- voltage, and the cut-off frequency, channel selectivity, and linearity of the proposed filter can be reconfigured accordingly. In order to improve the accuracy of the cut-off frequency, a binary-weigh- ted switched-capacitor array is employed as the auto-tuning circuits to calibrate the RC-time con- stant. Fabricated in TSMC 0. 18μm RF CMOS process, the proposed LPF achieves a measured cutoff frequency of 1.95 and 12.3MHz for WCDMA and GPS/Galileo application with a bandwidth de viation less than 4%. The measured l dB compression points are -3.0dBm and -5.1 dBm respectively for different modes. The core circuit of LPF consumes l mW and 1.6mW for WCDMA and GPS/Galileo respectively. And the proposed LPF occupies an area of 0.78ram2.展开更多
This article presents a high speed third-order continuous-time(CT)sigma-delta analog-to-digital converter(SDADC)based on voltagecontrolled oscillator(VCO),featuring a digital programmable quantizer structure.To improv...This article presents a high speed third-order continuous-time(CT)sigma-delta analog-to-digital converter(SDADC)based on voltagecontrolled oscillator(VCO),featuring a digital programmable quantizer structure.To improve the overall performance,not only oversampling technique but also noise-shaping enhancing technique is used to suppress in-band noise.Due to the intrinsic first-order noise-shaping of the VCO quantizer,the proposed third-order SDADC can realize forth-order noise-shaping ideally.As a bright advantage,the proposed programmable VCO quantizer is digital-friendly,which can simplify the design process and improve antiinterference capability of the circuit.A 4-bit programmable VCO quantizer clocked at 2.5 GHz,which is proposed in a 40 nm complementary metaloxide semiconductor(CMOS)technology,consists of an analog VCO circuit and a digital programmable quantizer,achieving 50.7 dB signal-to-noise ratio(SNR)and 26.9 dB signal-to-noise-and-distortion ration(SNDR)for a 19 MHz−3.5 dBFS input signal in 78 MHz bandwidth(BW).The digital quantizer,which is programmed in the Verilog hardware description language(HDL),consists of two-stage D-flip-flop(DFF)based registers,XOR gates and an adder.The presented SDADC adopts the cascade of integrators with feed-forward summation(CIFF)structure with a third-order loop filter,operating at 2.5 GHz and showing behavioral simulation performance of 92.9 dB SNR over 78 MHz bandwidth.展开更多
A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is cho...A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is chosen to get 50 Ohm impedance matching at the input. The noise contribution of common gate transistor is analyzed for the first time. The designed LNA is verified with IBM silicon-germanium(SiGe ) 0. 13μm BiCMOS process. The measured results show that the designed LNA has the gain of 13 dB and NF of 2. 8 dB at the center frequency of 5. 5 GHz. The input reflection S11 and output reflection S22 are equal to-19 dB and-11 dB respectively. The P-1 dB and IIP3 are-8. 9 dBm and 6. 6 dBm for the linearity performance respectively. The power consumption is only 1. 3 mW under the 1. 2 V supply. LNA achieves high gain,low noise,and high linearity performance,allowing it to be used for the WLAN 802. 11 ac applications.展开更多
Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter applic...Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter application is presented in this paper. Two TI-EF-DSMs are compared,one is a conventional directly implemented and the other is the improved. The processing speed of the proposed two-channel improved time-interleaved error feedback delta sigma modulator( ITI-EF-DSM) is higher than the conventional directly implemented TI-EF-DSM for shortened critical path. A digital transmitter based on the ITI-EF-DSM is implemented on field progrmmable gate array( FPGA). The long term evolution( LTE) signals with different bandwidths of 5 MHz,10 MHz and 20 MHz are used as the signal source to evaluate the transmitter. The achieved SNR is 41 dB for the 20 MHz LTE signal with the processing clock of only 184 MHz.展开更多
A low noise distributed amplifier consisting of 9 gain cells is presented.The chip is fabricated with 0.15-μm GaAs pseudomorphic high electron mobility transistor（PHEMT） technology from Win Semiconductor of Taiwan....A low noise distributed amplifier consisting of 9 gain cells is presented.The chip is fabricated with 0.15-μm GaAs pseudomorphic high electron mobility transistor（PHEMT） technology from Win Semiconductor of Taiwan.A special optional gate bias technique is introduced to allow an adjustable gain control range of 10 dB.A novel cascode structure is adopted to extend the output voltage and bandwidth.The measurement results show that the amplifier gives an average gain of 15 dB with a gain flatness of±1 dB in the 2-20 GHz band.The noise figure is between 2 and 4.1 dB during the band from 2 to 20 GHz.The amplifier also provides 13.8 dBm of output power at a 1 dB gain compression point and 10.5 dBm of input third order intercept point（IIP3）,which demonstrates the excellent performance of linearity.The power consumption is 300 mW with a supply of 5 V,and the chip area is 2.36×1.01 mm^2.展开更多
This paper presents a wideband low noise amplifier （LNA） for multi-standard radio applications. The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gate- indu...This paper presents a wideband low noise amplifier （LNA） for multi-standard radio applications. The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gate- inductive-peaking technique. High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band. Fabricated in 0.18 μm CMOS process, the LNA achieves 2.5 GHz of -3 dB bandwidth and 16 dB of gain. The gain variation is within 4-0.8 dB from 300 MHz to 2.2 GHz. The measured noise figure （NF） and average IIP3 are 3.4 dB and -2 dBm, respectively. The proposed LNA occupies 0.39 mm2 core chip area. Operating at 1.8 V, the LNA drains a current of 11.7 mA.展开更多
This paper presents a differential low power low noise amplifier designed for the wireless sensor network （WSN） in a TSMC 0.18μm RF CMOS process.A two-stage cross-coupling cascaded common-gate（CG） topology has be...This paper presents a differential low power low noise amplifier designed for the wireless sensor network （WSN） in a TSMC 0.18μm RF CMOS process.A two-stage cross-coupling cascaded common-gate（CG） topology has been designed as the amplifier.The first stage is a capacitive cross-coupling topology.It can reduce the power and noise simultaneously.The second stage is a positive feedback cross-coupling topology,used to set up a negative resistance to enhance the equivalent Q factor of the inductor at the load to improve the gain of the LNA.A differential inductor has been designed as the load to achieve reasonable gain.This inductor has been simulated by the means of momentum electromagnetic simulation in ADS.A ＂double-π＂ circuit model has been built as the inductor model by iteration in ADS.The inductor has been fabricated separately to verify the model. The LNA has been fabricated and measured.The LNA works well centered at 2.44 GHz.The measured gain S_（21） is variable with high gain at 16.8 dB and low gain at 1 dB.The NF（noise figure） at high gain mode is 3.6 dB,the input referenced 1 dB compression point（IP1dB） is about -8 dBm and the IIP3 is 2 dBm at low gain mode.The LNA consumes about 1.2 mA current from 1.8 V power supply.展开更多
A fully integrated 40 Gbit/s optical receiver analog front-end （AFE） including a transimpedance amplifier （TIA） and a limiting amplifier （LA） for short distance communication is described in this paper. The prop...A fully integrated 40 Gbit/s optical receiver analog front-end （AFE） including a transimpedance amplifier （TIA） and a limiting amplifier （LA） for short distance communication is described in this paper. The proposed TIA employs a modified regulated cascode （RGC） configuration as input stage, and adopts a third order interleaving active feedback gain stage. The LA utilizes nested active feedback, negative capacitance, and inductor peaking technology to achieve high voltage gain and wide bandwidth. The tiny photo current received by the receiver AFE is amplified to a single-ended voltage swing of 200 mV（p-p）. Simulation results show that the receiver AFE provides conversion gain of up to 83 dBΩ and bandwidth of 34.7 GHz, and the equivalent input noise current integrated from 1 MHz to 30 GHz is about 6.6 μA（rms）.展开更多
This paper compares model differences of transformers measured in 4-port and 2-port configurations. Although 2-port configuration is more appropriate for measurement and application, it brings tremendous difficul- tie...This paper compares model differences of transformers measured in 4-port and 2-port configurations. Although 2-port configuration is more appropriate for measurement and application, it brings tremendous difficul- ties to the model＇s parameter extraction. In this paper, a physics-based equivalent circuit model and its correspond- ing direct extraction procedure are proposed for on-chip transformers. The extraction is based on the measurement of 2-port configuration instead of the 4-port type, and it can capture the model parameters without any optimiza- tion. In this procedure, a new method has been developed for the parameter extraction of the ladder circuit, which is commonly used to represent the skin effect. Thus, this method can be transferred to the modeling of other passive devices, such as on-chip transmission lines, inductors, baluns, etc. In order to verify the procedure＇s efficiency and accuracy, an on-chip interleaved transformer in a 90 nm 1P9M CMOS process has been fabricated. We compare the modeled and measured self-inductance, the quality factor, mutual reactive and resistive coupling coefficients. Excellent agreement has been found over a broad frequency range.展开更多
A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb/s high-density ultra-high speed parallel optical communication system. With critical limitation...A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb/s high-density ultra-high speed parallel optical communication system. With critical limitations on power consumption, area and fabrication cost, the preamplifier achieves high performance, e.g. high bandwidth, high trans-impedance gain, low noise and high stability. A novel feed-forward common gate （FCG） stage is adopted to alleviate contradictions on trans-impedance gain and bandwidth by using a low headroom con- suming approach to isolate a large input capacitance and using complex pole peaking techniques to substitute induc- tors to achieve bandwidth extension. A multi-supply power-configurable scheme was employed to avoid wasteful power caused by a pessimistic estimation of process-voltage-temperature （PVT） variation. Two representative sam- ples provide a trans-impedance gain of 53.9 dBf2, a 3-dB bandwidth of 6.8 GHz, a power dissipation of 6.26 mW without power-configuration and a trans-impedance gain of 52.1 dBg2, a 3-dB bandwidth of 8.1 GHz, a power dis- sipation of 6.35 mW with power-configuration, respectively. The measured average input-referred noise-current spectral density is no more than 28 pA/√Hz. The chip area is only 0.08 x 0.08 mm2.展开更多
This paper presents a 10 bit successive approximation register （SAR） analog-to-digital converter （ADC） in 0.18 μm 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split...This paper presents a 10 bit successive approximation register （SAR） analog-to-digital converter （ADC） in 0.18 μm 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter （DAC）. In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio （SNDR） of 57.5 dB and spurious-free dynamic range （SFDR） of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm2.展开更多
A 53 GHz Colpitts oscillator implemented in a SiGe：C BiCMOS technology is presented. Limited by a 26.5 GHz frequency analyzer, the oscillator was measured indirectly through an on-chip mixer. The mixer downconverted ...A 53 GHz Colpitts oscillator implemented in a SiGe：C BiCMOS technology is presented. Limited by a 26.5 GHz frequency analyzer, the oscillator was measured indirectly through an on-chip mixer. The mixer downconverted the oscillating frequency to an intermediate frequency （IF） below 26.5 GHz. By adjusting the local oscillating （LO） frequency and recording the changes of IF frequency, the oscillator＇s output frequency （RF） was determined. Additionally, using phase noise theory of mixers, the oscillator＇s phase noise was estimated as -58 dBc/Hz at 1 MHz offset and the output power was about -21 dBm. The chip is 270 ×480μm in size.展开更多
基金supported by the National Natural Science Foundation of China,No.90307013,90707005a grant from the Science&Technology Pillar Program of Jiangsu Province in China,No.BE2013706
文摘Hemiparesis is one of the most common consequences of stroke. Advanced rehabilitation techniques are essential for restoring motor function in hemiplegic patients. Functional electrical stimulation applied to the affected limb based on myoelectric signal from the unaffected limb is a promising therapy for hemiplegia. In this study, we developed a prototype system for evaluating this novel functional electrical stimulation-control strategy. Based on surface electromyography and a vector machine model, a self-administered, muki-movement, force-modulation functional electrical stimulation-prototype system for hemiplegia was implemented. This paper discusses the hardware design, the algorithm of the system, and key points of the self-oscillation-prone system. The experimental results demonstrate the feasibility of the prototype system for further clinical trials, which is being conducted to evaluate the efficacy of the proposed rehabilitation technique.
基金Supported by the National Natural Science Foundation of China(No.61534003,61874024,61871116)
文摘The paper presents a fully integrated ultra-wide band(UWB)low noise amplifier(LNA)for 3-10 GHz applications.It employs self-biased resistive-feedback and current-reused technique to achieve wide input matching and low power characteristics.An improved biased architecture is adopted in the second stage to attain a better gain-compensation performance.The design is verified with TSMC standard 1 P6 M 0.18μm RF CMOS process.The measurement results show that the parasitic problem of the transistors at high frequencies is solved.A high and flat S21 of 9.7±1.5 dB and the lowest NF 3.5 dB are achieved in the desired frequency band.The power consumption is only 7.5 mA under 1.6 V supply.The proposed LNA achieves broadband flat gain,low noise,and high linearity performance simultaneously,allowing it to be used in 3-10 GHz UWB applications.
基金Supported by the National Natural Science Foundation of China （No. 60576028） and the National High Technology Research and Development Program of China （No. 2007AA01Z2a5）
文摘To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural networks （ANN） hardware implementation methods, a bit-stream ANN construction method based on direct sigma-delta （Z-A） signal processing is presented. The bit-stream adder, multiplier and fully digital X-A modulator used in the bit-stream linear ANN are implemented in a field programmable gate array （FPGA）. A bit-stream linear ANN based on these bit-stream modules is presented and implemented. To verify the function and performance of the bit-stream linear ANN, the bit-stream adaptive predictor and the bit-stream adaptive noise cancellation system are presented. The predicted result of the bit-stream adaptive predictor is very close to the desired signal. Also, the bit-stream adaptive noise cancellation system removes the electric power noise effectively.
基金The National Natural Science Foundation of China(No.61306069)
文摘A 12-Gbit/s low-power,wide-bandwidh CMOS(complementary metal oxide semiconductor)dual negative feedback feed-forward common gate(DNFFCG)differential trans-impedance amplifier(TIA)is presented for the veryshort-reach(VSR)optoelectronic integrated circuit(OEIC)receiver.The dominant pole of the input node is shifted up to a high frequency,and thus the bandwidth of the CMOS DNFFCG TIA is improved.Besides,two negative feedback loops are used to reduce the input impedance and further increase the bandwidth.The proposed TIA was fabricated using TSMC 0.18 jxm CMOS technology.The whole circuit has a compact chip area,the core area of which is only 0.003 6 mm2.The power consumption is 14.6 mW excluding 2-stage differential buffers.The test results indicate that the 3 dB bandwidth of 9 GHz is achieved with a 1 8 V supply voltage and its trans-impedance gain is 49.2 dBH.The measured average equivalent input noise current density is 28.1 pA H z12.Under the same process conditions,the DNFFCG has better gain bandwidth product compared with those in the published papers.
基金supported by the National Natural Science Foundation of China,No.90307013,90707005,61534003the Science&Technology Pillar Program of Jiangsu Province in China,No.BE2013706
文摘Voluntary participation of hemiplegic patients is crucial for functional electrical stimulation therapy.A wearable functional electrical stimulation system has been proposed for real-time volitional hand motor function control using the electromyography bridge method.Through a series of novel design concepts,including the integration of a detecting circuit and an analog-to-digital converter,a miniaturized functional electrical stimulation circuit technique,a low-power super-regeneration chip for wireless receiving,and two wearable armbands,a prototype system has been established with reduced size,power,and overall cost.Based on wrist joint torque reproduction and classification experiments performed on six healthy subjects,the optimized surface electromyography thresholds and trained logistic regression classifier parameters were statistically chosen to establish wrist and hand motion control with high accuracy.Test results showed that wrist flexion/extension,hand grasp,and finger extension could be reproduced with high accuracy and low latency.This system can build a bridge of information transmission between healthy limbs and paralyzed limbs,effectively improve voluntary participation of hemiplegic patients,and elevate efficiency of rehabilitation training.
基金Supported by the National Natural Science Foundation of China(No.61674037)National Key Research and Development Program of China(No.2016YFC0800400)the Priority Academic Program Development of Jiangsu Higher Education Institutions
文摘A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circuit, is adopted to reduce the frequency division step. The NF-DSM, which can obtain smooth output spectra, is proposed to generate the fractional part of the division ratio, moreover, the integer part of the division ratio is realized by a divider-by-2/3 circuit chain. Fabricated in TSMC 0.18 μm RF CMOS technology, the fractional frequency divider achieves a measured operation frequency from 0.5 GHz to 8 GHz. With a 1.8 V supply voltage, the maximum current consumption of the whole divider is 17.5 mA, and the chip area is 0.58 mm^2, including the pads.
基金Supported by the National Natural Science Foundation of China(No.61674037)National Major Special Plan of China(No.2018ZX03001008-002)the Double First-Class University and Disciplines Project of China。
文摘A fully integrated wideband voltage-controlled-oscillator(VCO) based on current-reused topology is presented. The overall scheme contains two sub-VCOs, which are controlled by a switch to cover a wide output frequency range. Fabricated in TSMC 65 nm CMOS technology, the measured output frequency of the VCO ranges from 3.991 GHz to 9.713 GHz,achieving a tuning range of 83.5%. And the worst and best phase noise at 1 MHz offset are-93.09 dBc/Hz and-111.97 dBc/Hz, respectively. With a 1.2 V supply voltage, the VCO core consumes a current of 3.7-5.1 mA across the entire frequency range. The chip area is 0.51 mm^2, including the pads. Moreover, the proposed VCO provides a figure-of-merit-with-tuning-range(FOM_T) of-191 dBc/Hz to-197 dBc/Hz.
基金supported by the National Natural Science Foundation of China,Nos.61534003 (to ZGW) and 61874024 (to ZGW)。
文摘Epidural stimulation of the spinal cord is a promising technique for the recovery of motor function after spinal cord injury.The key challenges within the reconstruction of motor function for paralyzed limbs are the precise control of sites and parameters of stimulation.To activate lower-limb muscles precisely by epidural spinal cord stimulation,we proposed a high-density,flexible electrode array.We determined the regions of motor function that were activated upon epidural stimulation of the spinal cord in a rat model with complete spinal cord,which was established by a transection method.For evaluating the effect of stimulation,the evoked potentials were recorded from bilateral lowerlimb muscles,including the vastus lateralis,semitendinosus,tibialis anterior,and medial gastrocnemius.To determine the appropriate stimulation sites and parameters of the lower muscles,the stimulation characteristics were studied within the regions in which motor function was activated upon spinal cord stimulation.In the vastus lateralis and medial gastrocnemius,these regions were symmetrically located at the lateral site of L1 and the medial site of L2 vertebrae segment,respectively.The tibialis anterior and semitendinosus only responded to stimulation simultaneously with other muscles.The minimum and maximum stimulation threshold currents of the vastus lateralis were higher than those of the medial gastrocnemius.Our results demonstrate the ability to identify specific stimulation sites of lower muscles using a high-density and flexible array.They also provide a reference for selecting the appropriate conditions for implantable stimulation for animal models of spinal cord injury.This study was approved by the Animal Research Committee of Southeast University,China(approval No.20190720001) on July 20,2019.
基金Supported by the National Basic Research Program of China(No.2010CB327404)the Priority Academic Program Development of Jiangsu Higher Education Institutions
文摘A 4th-order low-pass filter （LPF） based on active-Gm-RC structure for multi-standard system application is presented in this paper. The performances of LPF are controlled by a 1-bit control- voltage, and the cut-off frequency, channel selectivity, and linearity of the proposed filter can be reconfigured accordingly. In order to improve the accuracy of the cut-off frequency, a binary-weigh- ted switched-capacitor array is employed as the auto-tuning circuits to calibrate the RC-time con- stant. Fabricated in TSMC 0. 18μm RF CMOS process, the proposed LPF achieves a measured cutoff frequency of 1.95 and 12.3MHz for WCDMA and GPS/Galileo application with a bandwidth de viation less than 4%. The measured l dB compression points are -3.0dBm and -5.1 dBm respectively for different modes. The core circuit of LPF consumes l mW and 1.6mW for WCDMA and GPS/Galileo respectively. And the proposed LPF occupies an area of 0.78ram2.
基金This work was supported by the Natural Science Foundation of the Jiangsu Higher Education Institutions of China under Grant No.18KJB510045.
文摘This article presents a high speed third-order continuous-time(CT)sigma-delta analog-to-digital converter(SDADC)based on voltagecontrolled oscillator(VCO),featuring a digital programmable quantizer structure.To improve the overall performance,not only oversampling technique but also noise-shaping enhancing technique is used to suppress in-band noise.Due to the intrinsic first-order noise-shaping of the VCO quantizer,the proposed third-order SDADC can realize forth-order noise-shaping ideally.As a bright advantage,the proposed programmable VCO quantizer is digital-friendly,which can simplify the design process and improve antiinterference capability of the circuit.A 4-bit programmable VCO quantizer clocked at 2.5 GHz,which is proposed in a 40 nm complementary metaloxide semiconductor(CMOS)technology,consists of an analog VCO circuit and a digital programmable quantizer,achieving 50.7 dB signal-to-noise ratio(SNR)and 26.9 dB signal-to-noise-and-distortion ration(SNDR)for a 19 MHz−3.5 dBFS input signal in 78 MHz bandwidth(BW).The digital quantizer,which is programmed in the Verilog hardware description language(HDL),consists of two-stage D-flip-flop(DFF)based registers,XOR gates and an adder.The presented SDADC adopts the cascade of integrators with feed-forward summation(CIFF)structure with a third-order loop filter,operating at 2.5 GHz and showing behavioral simulation performance of 92.9 dB SNR over 78 MHz bandwidth.
基金Supported by the National Natural Science Foundation of China(No.61534003)
文摘A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is chosen to get 50 Ohm impedance matching at the input. The noise contribution of common gate transistor is analyzed for the first time. The designed LNA is verified with IBM silicon-germanium(SiGe ) 0. 13μm BiCMOS process. The measured results show that the designed LNA has the gain of 13 dB and NF of 2. 8 dB at the center frequency of 5. 5 GHz. The input reflection S11 and output reflection S22 are equal to-19 dB and-11 dB respectively. The P-1 dB and IIP3 are-8. 9 dBm and 6. 6 dBm for the linearity performance respectively. The power consumption is only 1. 3 mW under the 1. 2 V supply. LNA achieves high gain,low noise,and high linearity performance,allowing it to be used for the WLAN 802. 11 ac applications.
基金Supported by the National Natural Science Foundation of China(No.61674037)the National Key Research and Development Program of China(No.2016YFC0800400)+2 种基金the Priority Academic Program Development of Jiangsu Higher Education Institutionsthe National Power Grid Corp Science and Technology Project(No.SGTYHT/16-JS-198)the State Grid Nanjing Power Supply Company Project(No.1701052)
文摘Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter application is presented in this paper. Two TI-EF-DSMs are compared,one is a conventional directly implemented and the other is the improved. The processing speed of the proposed two-channel improved time-interleaved error feedback delta sigma modulator( ITI-EF-DSM) is higher than the conventional directly implemented TI-EF-DSM for shortened critical path. A digital transmitter based on the ITI-EF-DSM is implemented on field progrmmable gate array( FPGA). The long term evolution( LTE) signals with different bandwidths of 5 MHz,10 MHz and 20 MHz are used as the signal source to evaluate the transmitter. The achieved SNR is 41 dB for the 20 MHz LTE signal with the processing clock of only 184 MHz.
基金Project supported by the National Natural Science Foundation of China(No.61106021)the Chinese Postdoctoral Science Foundation(Nos. 20090461049.20090461048)the Innovation Fund of Ministry of Science & Technology for Small and Medium Sized Enterprises, China(No.11C26213211234)
文摘A low noise distributed amplifier consisting of 9 gain cells is presented.The chip is fabricated with 0.15-μm GaAs pseudomorphic high electron mobility transistor（PHEMT） technology from Win Semiconductor of Taiwan.A special optional gate bias technique is introduced to allow an adjustable gain control range of 10 dB.A novel cascode structure is adopted to extend the output voltage and bandwidth.The measurement results show that the amplifier gives an average gain of 15 dB with a gain flatness of±1 dB in the 2-20 GHz band.The noise figure is between 2 and 4.1 dB during the band from 2 to 20 GHz.The amplifier also provides 13.8 dBm of output power at a 1 dB gain compression point and 10.5 dBm of input third order intercept point（IIP3）,which demonstrates the excellent performance of linearity.The power consumption is 300 mW with a supply of 5 V,and the chip area is 2.36×1.01 mm^2.
基金Project Supported by the National Science and Technology Major Project of China(No.2009ZX03002-004)
文摘This paper presents a wideband low noise amplifier （LNA） for multi-standard radio applications. The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gate- inductive-peaking technique. High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band. Fabricated in 0.18 μm CMOS process, the LNA achieves 2.5 GHz of -3 dB bandwidth and 16 dB of gain. The gain variation is within 4-0.8 dB from 300 MHz to 2.2 GHz. The measured noise figure （NF） and average IIP3 are 3.4 dB and -2 dBm, respectively. The proposed LNA occupies 0.39 mm2 core chip area. Operating at 1.8 V, the LNA drains a current of 11.7 mA.
基金supported by the National High Technology Research and Development Program of China(No.2007AA01Z2A7)the Special Fund of Jiangsu Province for the Transformation of Scientific and Technological Achievements(No.BA2010073)
文摘This paper presents a differential low power low noise amplifier designed for the wireless sensor network （WSN） in a TSMC 0.18μm RF CMOS process.A two-stage cross-coupling cascaded common-gate（CG） topology has been designed as the amplifier.The first stage is a capacitive cross-coupling topology.It can reduce the power and noise simultaneously.The second stage is a positive feedback cross-coupling topology,used to set up a negative resistance to enhance the equivalent Q factor of the inductor at the load to improve the gain of the LNA.A differential inductor has been designed as the load to achieve reasonable gain.This inductor has been simulated by the means of momentum electromagnetic simulation in ADS.A ＂double-π＂ circuit model has been built as the inductor model by iteration in ADS.The inductor has been fabricated separately to verify the model. The LNA has been fabricated and measured.The LNA works well centered at 2.44 GHz.The measured gain S_（21） is variable with high gain at 16.8 dB and low gain at 1 dB.The NF（noise figure） at high gain mode is 3.6 dB,the input referenced 1 dB compression point（IP1dB） is about -8 dBm and the IIP3 is 2 dBm at low gain mode.The LNA consumes about 1.2 mA current from 1.8 V power supply.
基金supported by the National Natural Science Foundation of China (60976029)
文摘A fully integrated 40 Gbit/s optical receiver analog front-end （AFE） including a transimpedance amplifier （TIA） and a limiting amplifier （LA） for short distance communication is described in this paper. The proposed TIA employs a modified regulated cascode （RGC） configuration as input stage, and adopts a third order interleaving active feedback gain stage. The LA utilizes nested active feedback, negative capacitance, and inductor peaking technology to achieve high voltage gain and wide bandwidth. The tiny photo current received by the receiver AFE is amplified to a single-ended voltage swing of 200 mV（p-p）. Simulation results show that the receiver AFE provides conversion gain of up to 83 dBΩ and bandwidth of 34.7 GHz, and the equivalent input noise current integrated from 1 MHz to 30 GHz is about 6.6 μA（rms）.
基金Project supported by the Yangzi-Delta Cooperative Projects of Zhejiang Province,China
文摘This paper compares model differences of transformers measured in 4-port and 2-port configurations. Although 2-port configuration is more appropriate for measurement and application, it brings tremendous difficul- ties to the model＇s parameter extraction. In this paper, a physics-based equivalent circuit model and its correspond- ing direct extraction procedure are proposed for on-chip transformers. The extraction is based on the measurement of 2-port configuration instead of the 4-port type, and it can capture the model parameters without any optimiza- tion. In this procedure, a new method has been developed for the parameter extraction of the ladder circuit, which is commonly used to represent the skin effect. Thus, this method can be transferred to the modeling of other passive devices, such as on-chip transmission lines, inductors, baluns, etc. In order to verify the procedure＇s efficiency and accuracy, an on-chip interleaved transformer in a 90 nm 1P9M CMOS process has been fabricated. We compare the modeled and measured self-inductance, the quality factor, mutual reactive and resistive coupling coefficients. Excellent agreement has been found over a broad frequency range.
基金Project supported by the National Natural Science Foundation of China(No.61106024)the Natural Science Foundation of Jiangsu Provice,China(No.BK2010411)
文摘A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb/s high-density ultra-high speed parallel optical communication system. With critical limitations on power consumption, area and fabrication cost, the preamplifier achieves high performance, e.g. high bandwidth, high trans-impedance gain, low noise and high stability. A novel feed-forward common gate （FCG） stage is adopted to alleviate contradictions on trans-impedance gain and bandwidth by using a low headroom con- suming approach to isolate a large input capacitance and using complex pole peaking techniques to substitute induc- tors to achieve bandwidth extension. A multi-supply power-configurable scheme was employed to avoid wasteful power caused by a pessimistic estimation of process-voltage-temperature （PVT） variation. Two representative sam- ples provide a trans-impedance gain of 53.9 dBf2, a 3-dB bandwidth of 6.8 GHz, a power dissipation of 6.26 mW without power-configuration and a trans-impedance gain of 52.1 dBg2, a 3-dB bandwidth of 8.1 GHz, a power dis- sipation of 6.35 mW with power-configuration, respectively. The measured average input-referred noise-current spectral density is no more than 28 pA/√Hz. The chip area is only 0.08 x 0.08 mm2.
基金supported by the National Natural Science Foundation of China(No.61401097)
文摘This paper presents a 10 bit successive approximation register （SAR） analog-to-digital converter （ADC） in 0.18 μm 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter （DAC）. In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio （SNDR） of 57.5 dB and spurious-free dynamic range （SFDR） of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm2.
文摘A 53 GHz Colpitts oscillator implemented in a SiGe：C BiCMOS technology is presented. Limited by a 26.5 GHz frequency analyzer, the oscillator was measured indirectly through an on-chip mixer. The mixer downconverted the oscillating frequency to an intermediate frequency （IF） below 26.5 GHz. By adjusting the local oscillating （LO） frequency and recording the changes of IF frequency, the oscillator＇s output frequency （RF） was determined. Additionally, using phase noise theory of mixers, the oscillator＇s phase noise was estimated as -58 dBc/Hz at 1 MHz offset and the output power was about -21 dBm. The chip is 270 ×480μm in size.
