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Toward High Carrier Mobility and Low Contact Resistance:Laser Cleaning of PMMA Residues on Graphene Surfaces 被引量:3
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作者 Yuehui Jia Xin Gong +5 位作者 Pei Peng Zidong Wang Zhongzheng Tian Liming Ren Yunyi Fu Han Zhang 《Nano-Micro Letters》 SCIE EI CAS 2016年第4期336-346,共11页
Poly(methyl methacrylate)(PMMA) is widely used for graphene transfer and device fabrication.However,it inevitably leaves a thin layer of polymer residues after acetone rinsing and leads to dramatic degradation of devi... Poly(methyl methacrylate)(PMMA) is widely used for graphene transfer and device fabrication.However,it inevitably leaves a thin layer of polymer residues after acetone rinsing and leads to dramatic degradation of device performance.How to eliminate contamination and restore clean surfaces of graphene is still highly demanded.In this paper,we present a reliable and position-controllable method to remove the polymer residues on graphene films by laser exposure.Under proper laser conditions,PMMA residues can be substantially reduced without introducing defects to the underlying graphene.Furthermore,by applying this laser cleaning technique to the channel and contacts of graphene fieldeffect transistors(GFETs),higher carrier mobility as well as lower contact resistance can be realized.This work opens a way for probing intrinsic properties of contaminant-free graphene and fabricating high-performance GFETs with both clean channel and intimate graphene/metal contact. 展开更多
关键词 GRAPHENE PMMA residues Laser exposure Carrier mobility Contact resistance
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Design and test results of a low-noise readout integrated circuit for high-energy particle detectors 被引量:1
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作者 ZHANG Mingming CHEN Zhongjian ZHANG Yacong LU Wengao JI Lijiu 《Nuclear Science and Techniques》 SCIE CAS CSCD 2010年第1期44-48,共5页
A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuo... A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuous-time semi-Gaussian filter is chosen to avoid switch noise.The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application.The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology.Test results show the functions of the readout integrated circuit are correct.The equivalent noise charge with no detector connected is 500–700 e in the typical mode,the gain is tunable within 13–130 mV/fC and the peaking time varies from 0.7 to 1.6 μs,in which the average gain is about 20.5 mV/fC,and the linearity reaches 99.2%. 展开更多
关键词 读出集成电路 高能粒子探测器 低噪声 设计 测试 CMOS工艺 峰值时间 单端放大器
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Structure-dependent behaviors of diode-triggered silicon controlled rectifier under electrostatic discharge stress 被引量:1
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作者 张立忠 王源 何燕冬 《Chinese Physics B》 SCIE EI CAS CSCD 2016年第12期507-513,共7页
The comprehensive understanding of the structure-dependent electrostatic discharge behaviors in a conventional diode-triggered silicon controlled rectifier (DTSCR) is presented in this paper. Combined with the devic... The comprehensive understanding of the structure-dependent electrostatic discharge behaviors in a conventional diode-triggered silicon controlled rectifier (DTSCR) is presented in this paper. Combined with the device simulation, a mathematical model is built to get a more in-depth insight into this phenomenon. The theoretical studies are verified by the transmission-line-pulsing (TLP) test results of the modified DTSCR structure, which is realized in a 65-nm complementary metal-oxide-semiconductor (CMOS) process. The detailed analysis of the physical mechanism is used to provide predictions as the DTSCR-based protection scheme is required. In addition, a method is also presented to achieve the tradeoff between the leakage and trigger voltage in DTSCR. 展开更多
关键词 electrostatic discharge (ESD) diode-triggered silicon controlled rectifier (DTSCR) transmission-line-pulsing (TLP) mathematical modeling
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Impact of nitrogen plasma passivation on the interface of germanium MOS capacitor
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作者 云全新 黎明 +9 位作者 安霞 林猛 刘朋强 李志强 张冰馨 夏宇轩 张浩 张兴 黄如 王阳元 《Chinese Physics B》 SCIE EI CAS CSCD 2014年第11期616-619,共4页
Nitrogen plasma passivation (NPP) on (111) germanium (Ge) was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition (PECVD).... Nitrogen plasma passivation (NPP) on (111) germanium (Ge) was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition (PECVD). The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interracial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness (EOT) scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process. 展开更多
关键词 GERMANIUM ROUGHNESS interface trap density interfacial layer thickness
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Experimental clarification of orientation dependence of germanium PMOSFETs with Al_2O_3/GeO_x/Ge gate stack
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作者 云全新 黎明 +9 位作者 安霞 林猛 刘朋强 李志强 张冰馨 夏宇轩 张浩 张兴 黄如 王阳元 《Chinese Physics B》 SCIE EI CAS CSCD 2014年第11期626-629,共4页
An extensive and complete experimental investigation with a full layout design of the channel direction was carried out for the first time to clarify the orientation dependence of germanium p-channel metal-oxide-semic... An extensive and complete experimental investigation with a full layout design of the channel direction was carried out for the first time to clarify the orientation dependence of germanium p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs). By comparison of gate trans-conductance, drive current, and hole mobility, we found that the performance trend with the substrate orientation for Ge PMOSFET is (110)〉(111) ~ (100), and the best channel direction is (110)/[110]. Moreover, the (110) device performance was found to be easily degraded as the channel direction got off from the [ 110] orientation, while (100) and (111) devices exhibited less channel orientation dependence. This experimental result shows good matching with the simulation reports to give a credible and significant guidance for Ge PMOSFET design. 展开更多
关键词 GERMANIUM metal-oxide-semiconductor field-effect transistor ORIENTATION
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Valence band variation in Si(110) nanowire induced by a covered insulator
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作者 许洪华 刘晓彦 +5 位作者 何毓辉 樊春 杜刚 孙爱东 韩汝琦 康晋锋 《Chinese Physics B》 SCIE EI CAS CSCD 2010年第1期398-402,共5页
In this work, we investigate strain effects induced by the deposition of gate dielectrics on the valence band structures in Si (110) nanowire via the simulation of strain distribution and the calculation of a genera... In this work, we investigate strain effects induced by the deposition of gate dielectrics on the valence band structures in Si (110) nanowire via the simulation of strain distribution and the calculation of a generalized 6 × 6k .p strained valence band. The nanowire is surrounded by the gate dielectric. Our simulation indicates that the strain of the amorphous SiO2 insulator is negligible without considering temperature factors. On the other hand, the thermal residual strain in a nanowire with amorphous SiO2 insulator which has negligible lattice misfit strain pushes the valence subbands upwards by chemical vapour deposition and downwards by thermal oxidation treatment. In contrast with the strain of the amorphous SiO2 insulator, the strain of the HfO2 gate insulator in Si (110) nanowire pushes the valence subbands upwards remarkably. The thermal residual strain by HfO2 insulator contributes to the up-shifting tendency. Our simulation results for valence band shifting and warping in Si nanowires can provide useful guidance for further nanowire device design. 展开更多
关键词 silicon nanowire valence band thermal residual strain
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Memory materials and devices:From concept to application 被引量:27
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作者 Zhenhan Zhang Zongwei Wang +6 位作者 Tuo Shi Chong Bi Feng Rao Yimao Cai Qi Liu Huaqiang Wu Peng Zhou 《InfoMat》 SCIE CAS 2020年第2期261-290,共30页
Memory cells have always been an important element of information technology.With emerging technologies like big data and cloud computing,the scale and complexity of data storage has reached an unprecedented peak with... Memory cells have always been an important element of information technology.With emerging technologies like big data and cloud computing,the scale and complexity of data storage has reached an unprecedented peak with a much higher requirement for memory technology.As is well known,better data storage is mostly achieved by miniaturization.However,as the size of the memory device is reduced,a series of problems,such as drain gate-induced leakage,greatly hinder the performance of memory units.To meet the increasing demands of information technology,novel and high-performance memory is urgently needed.Fortunately,emerging memory technologies are expected to improve memory performance and drive the information revolution.This review will focus on the progress of several emerging memory technologies,including two-dimensional material-based memories,resistance random access memory(RRAM),magnetic random access memory(MRAM),and phasechange random access memory(PCRAM).Advantages,mechanisms,and applications of these diverse memory technologies will be discussed in this review. 展开更多
关键词 MEMORY MRAM PCRAM RRAM two-dimensional material
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Fabricating GeO_2 passivation layer by N_2O plasma oxidation for Ge NMOSFETs application 被引量:1
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作者 林猛 安霞 +6 位作者 黎明 云全新 李敏 李志强 刘朋强 张兴 黄如 《Chinese Physics B》 SCIE EI CAS CSCD 2014年第6期538-541,共4页
In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that 1.0-nm GeO2 is achieved after 120-s N20 plasma oxidation at 300 ℃. The GeO2/Ge interface is atomica... In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that 1.0-nm GeO2 is achieved after 120-s N20 plasma oxidation at 300 ℃. The GeO2/Ge interface is atomically smooth. The interface state density of Ge surface after N20 plasma passivation is about - 3 × 1011 cm-2.eV-1. With GeO2 passivation, the hysteresis of metal-oxide-semiconductor (MOS) capacitor with A1203 serving as gate dielectric is reduced to - 50 mV, compared with - 130 mV of the untreated one. The Fermi-level at GeO2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage. 展开更多
关键词 Ge GeO2 passivation N2O plasma oxidation Ge NMOSFETs
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Effects of heavy ion irradiation on ultra-deep-submicron partially-depleted SOI devices 被引量:1
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作者 武唯康 安霞 +5 位作者 谭斐 冯慧 陈叶华 刘静静 张兴 黄如 《Journal of Semiconductors》 EI CAS CSCD 2015年第11期39-43,共5页
The effects of the physical damages induced by heavy ion irradiation on the performance of partiallydepleted SOI devices are experimentally investigated. After heavy ion exposure, different degradation phenomena are o... The effects of the physical damages induced by heavy ion irradiation on the performance of partiallydepleted SOI devices are experimentally investigated. After heavy ion exposure, different degradation phenomena are observed due to the random strike of heavy ions. A decrease of the saturation current and transconductance,and an enhanced gate-induced drain leakage current are observed, which are mainly attributed to the displacement damages that may be located in the channel, the depletion region of the drain/body junction or the gate-to-drain overlap region. Further, PDSOI devices with and without body contact are compared, which reveals the differences in the threshold voltage shift, the drain-induced barrier lowing effect, the transconductance and the kink effect. The results may provide a guideline for radiation hardened design. 展开更多
关键词 heavy ion displacement damages PDSOI performance degradation
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Phonon-Limited Electron Mobility in Single-Layer MoS2 被引量:1
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作者 曾琅 辛争 +3 位作者 陈少闻 杜刚 康晋锋 刘晓彦 《Chinese Physics Letters》 SCIE CAS CSCD 2014年第2期101-104,共4页
The dynamics of electron transport in single-layer MoS2 is simulated by employing the single particle Monte Carlo method. Acoustic phonon scattering, optical phonon scattering and Frohlich scattering are taken into ac... The dynamics of electron transport in single-layer MoS2 is simulated by employing the single particle Monte Carlo method. Acoustic phonon scattering, optical phonon scattering and Frohlich scattering are taken into account. It is found that the electron mobility decreases from 806cm2 /V.s for a transverse electrical field of 103 Vim to 426/112 cm2 /V.s for a transverse electrical field of 105/107 Vim. Further detailed analysis on carrier dynamics reveals that the low field mobility is dominated by the acoustic phonon scattering while the role of optical phonon scattering is to relax the electron energy below the optical phonon energy by efficient energy relaxation through optical phonon emission. Only when the transverse electrical field is larger than 106 V/m, the mobility can be determined by the optical phonon scattering, leading to a strong mobility degradation. 展开更多
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An oxide/silicon core/shell nanowire metal-oxide semiconductor field-effect transistor
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作者 张立宁 何进 +2 位作者 周旺 陈林 徐艺文 《Chinese Physics B》 SCIE EI CAS CSCD 2010年第4期398-401,共4页
This paper studies an oxide/silicon core/shell nanowire MOSFET (OS-CSNM). Through three-dimensional device simulations, we have demonstrated that the OS-CSNM has a lower leakage current and higher Ion/Ioff ratio aft... This paper studies an oxide/silicon core/shell nanowire MOSFET (OS-CSNM). Through three-dimensional device simulations, we have demonstrated that the OS-CSNM has a lower leakage current and higher Ion/Ioff ratio after intro- ducing the oxide core into a traditional nanowire MOSFET (TNM). The oxide/silicon OS-CSNM structure suppresses threshold voltage roll-off, drain induced barrier lowering and subthreshold swing degradation. Smaller intrinsic device delay is also observed in OS-CSNM in comparison with that of TNM. 展开更多
关键词 core/shell NANOWIRE nanowire MOSFET
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MXenes induce epitaxial growth of size-controlled noble nanometals:A case study for surface enhanced Raman scattering(SERS) 被引量:4
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作者 Renfei Cheng Tao Hu +11 位作者 Minmin Hu Changji Li Yan Liang Zuohua Wang Hui Zhang Muchan Li Hailong Wang Hongxia Lu Yunyi Fu Hongwang Zhang Quan-Hong Yang Xiaohui Wang 《Journal of Materials Science & Technology》 SCIE EI CAS CSCD 2020年第5期119-127,共9页
Noble nanometals are of significance in both scientific interest and technological applications,which are usually obtained by conventional wet-chemical synthesis.Organic surfactants are always used in the synthesis to... Noble nanometals are of significance in both scientific interest and technological applications,which are usually obtained by conventional wet-chemical synthesis.Organic surfactants are always used in the synthesis to prevent unexpected overgrowth and aggregation of noble nanometals.However,the surfactants are hard to remove and may interfere with plasmonic and catalytic studies,remaining surfactant-free synthesis of noble nanometals a challenge.Herein,we report an approach to epitaxial growth of sizecontrolled noble nanometals on MXenes.As piloted by density functional theory calculations,along with work function experimental determination,kinetic and spectroscopic studies,epitaxial growth of noble nanometals is initiated via a mechanism that involves an in situ redox reaction.In the redox,MXenes as two-dimensional solid reductants whose work functions are compatible with the reduction potentials of noble metal cations,enable spontaneous donation of electrons from the MXenes to noble metal cations and reduce the cations into nanoscale metallic metals on the outmost surface of MXenes.Neither surfactants nor external reductants are used during the whole synthesis process,which addresses a long-standing interference issue of surfactant and external reductant in the conventional wet-chemical synthesis.Moreover,the MXenes induced noble nanometals are size-controlled.Impressively,noble nanometals firmly anchored on MXenes exhibit excellent performance towards surface enhanced Raman scattering.Our developed strategy will promote the nanostructure-controlled synthesis of noble nanometals,offering new opportunities to further improve advanced functional properties towards practical applications. 展开更多
关键词 TWO-DIMENSIONAL materials MXene In SITU redox NOBLE METAL SERS
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A VCO sub-band selection circuit for fast PLL calibration
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作者 宋颖 王源 +1 位作者 贾嵩 赵宝瑛 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2009年第8期153-155,共3页
A novel voltage controlled oscillator (VCO) sub-band selection circuit to achieve fast phase locked loop (PLL) calibration is presented, which reduces the calibration time by measuring the period difference direct... A novel voltage controlled oscillator (VCO) sub-band selection circuit to achieve fast phase locked loop (PLL) calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implemented in a 0.18 μm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 μs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most. 展开更多
关键词 PLL VCO CALIBRATION
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Heavy ion induced electrical property degradation in sub-100 nm bulk silicon MOS devices
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作者 陈叶华 安霞 +4 位作者 武唯康 张曜 刘静静 张兴 黄如 《Journal of Semiconductors》 EI CAS CSCD 2015年第11期30-33,共4页
The radiation response of 90 nm bulk silicon MOS devices after heavy ion irradiation is experimentally investigated. Due to the random strike of the incident particle, different degradation behaviors of bulk silicon M... The radiation response of 90 nm bulk silicon MOS devices after heavy ion irradiation is experimentally investigated. Due to the random strike of the incident particle, different degradation behaviors of bulk silicon MOS devices are observed. The drain current and maximum transconductance degrade as a result of the displacement damage in the channel induced by heavy ion strike. The off-state leakage current degradation and threshold voltage shift are also observed after heavy ion irradiation. The results suggest that the radiation induced damage of sub-100 nm MOS devices caused by heavy ion irradiation should be paid attention. 展开更多
关键词 heavy ion displacement damage bulk silicon
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Contact size scaling of a W-contact phase-change memory cell based on numerical simulation
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作者 魏益群 林信南 +3 位作者 贾宇超 崔小乐 张兴 宋志棠 《Journal of Semiconductors》 EI CAS CSCD 2012年第10期53-57,共5页
In the design of phase-change memory(PCM),it is important to perform numerical simulations to predict the performances of different device structures.This work presents a numerical simulation using a coupled system ... In the design of phase-change memory(PCM),it is important to perform numerical simulations to predict the performances of different device structures.This work presents a numerical simulation using a coupled system including Poisson's equation,the current continuity equation,the thermal conductivity equation,and phase-change dynamics to simulate the thermal and electric characteristics of phase-change memory.This method discriminates the common numerical simulation of PCM cells,from which it applies Possion's equation and current continuity equations instead of the Laplace equation to depict the electric characteristics of PCM cells,which is more adoptable for the semiconductor characteristics of phase-change materials.The results show that the simulation agrees with the measurement,and the scalability of PCM is predicted. 展开更多
关键词 phase-change memory SCALING numerical simulation
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Line-edge roughness induced single event transient variation in SOI Fin FETs 被引量:1
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作者 武唯康 安霞 +4 位作者 蒋晓波 陈叶华 刘静静 张兴 黄如 《Journal of Semiconductors》 EI CAS CSCD 2015年第11期25-29,共5页
The impact of process induced variation on the response of SOI Fin FET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When Fin FET biased at OFF state configuration(Vgs D0, Vds DV... The impact of process induced variation on the response of SOI Fin FET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When Fin FET biased at OFF state configuration(Vgs D0, Vds DVdd/ is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse(single event transient, SET) is consequently formed. The results reveal that with the presence of line-edge roughness(LER), which is one of the major variation sources in nano-scale Fin FETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered: type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters,correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size. 展开更多
关键词 heavy ion irradiation single event transient VARIATION line-edge roughness SOI Fin FET
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Vertical‐organic‐nanocrystal‐arrays for crossbar memristors with tuning switching dynamics toward neuromorphic computing 被引量:6
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作者 Fangxu Yang Lingjie Sun +7 位作者 Qingxi Duan Huanli Dong Zhaokun Jing Yuchao Yang Rongjin Li Xiaotao Zhang Wenping Hu Leon Chua 《SmartMat》 2021年第1期99-108,共10页
Memristors proposed by Leon Chua provide a new type of memory device for novel neuromorphic computing applications.However,the approaching of distinct multi‐intermediate states for tunable switching dynamics,the con-... Memristors proposed by Leon Chua provide a new type of memory device for novel neuromorphic computing applications.However,the approaching of distinct multi‐intermediate states for tunable switching dynamics,the con-trolling of conducting filaments(CFs)toward high device repeatability and reproducibility,and the ability for large‐scale preparation devices,remain full of challenges.Here,we show that vertical‐organic‐nanocrystal‐arrays(VONAs)could make a way toward the challenges.The perfect one‐dimensional structure of the VONAs could confine the CFs accurately with fine‐tune resistance states in a broad range of 103 ratios.The availability of large‐area VONAs makes the fabrication of large‐area crossbar memristor arrays facilely,and the analog switching characteristic of the memristors is to effectively imitate different kinds of synaptic plasticity,indicating their great potential in future applications. 展开更多
关键词 conducting filament MEMRISTOR organic electronics organic single crystal
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Insight into multiple-triggering effect in DTSCRs for ESD protection 被引量:2
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作者 Lizhong Zhang Yuan Wang +1 位作者 Yize Wang Yandong He 《Journal of Semiconductors》 EI CAS CSCD 2017年第7期93-96,共4页
The diode-triggered silicon-controlled rectifier(DTSCR) is widely used for electrostatic discharge(ESD) protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigge... The diode-triggered silicon-controlled rectifier(DTSCR) is widely used for electrostatic discharge(ESD) protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigger/holding voltage, low parasitic capacitance. However, the multiple-triggering effect in the typical DTSCR device may cause undesirable larger overall trigger voltage, which results in a reduced ESD safe margin. In previous research, the major cause is attributed to the higher current level required in the intrinsic SCR. The related discussions indicate that it seems to result from the current division rule between the intrinsic and parasitic SCR formed in the triggering process. In this letter, inserting a large space into the trigger diodes is proposed to get a deeper insight into this issue. The triggering current is observed to be regularly reduced along with the increased space, which confirms that the current division is determined by the parasitic resistance distributed between the intrinsic and parasitic SCR paths. The theoretical analysis is well confirmed by device simulation and transmission line pulse(TLP) test results. The reduced overall trigger voltage is achieved in the modified DTSCR structures due to the comprehensive result of the parasitic resistance vs triggering current, which indicates a minimized multipletriggering effect. 展开更多
关键词 electrostatic discharge(ESD) diode-triggered silicon-controlled rectifier(DTSCR) double snapback transmission line pulse(TLP) test
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An improved single-loop sigma-delta modulator for GSM applications
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作者 李宏义 王源 +1 位作者 贾嵩 张兴 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第9期125-132,共8页
Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and d... Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system. 展开更多
关键词 sigma-delta modulator low-distortion CDS switched-capacitor circuit delayed input feedforward
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Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit
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作者 刘振 贾嵩 +2 位作者 王源 吉利久 张兴 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2009年第12期128-132,共5页
This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter (ADC) A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only... This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter (ADC) A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply. 展开更多
关键词 analog-to-digital converter low power fully-folding mixed-averaging distributed T/H circuit bit synchronization
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