期刊文献+
共找到2篇文章
< 1 >
每页显示 20 50 100
Statistical performance of IF estimation of LFM signals with timevarying amplitude using the peak of WVD 被引量:2
1
作者 Chen Guanghua Ma Shiwei Qin Tinghao Wang Jian Li Ming Cao Jialin 《Journal of Systems Engineering and Electronics》 SCIE EI CSCD 2005年第4期787-791,共5页
The instantaneous frequency (IF) estimation of the linear frequency modulated (LFM) signals with time-varying amplitude using the peak of the Wigner-Ville distribution (WVD) is studied. Theoretical analysis show... The instantaneous frequency (IF) estimation of the linear frequency modulated (LFM) signals with time-varying amplitude using the peak of the Wigner-Ville distribution (WVD) is studied. Theoretical analysis shows that the estimation on LFM signals with time-varying amplitude is unbiased, only if WVD of time-varying amplitude reaches its maximum at frequency zero no matter in which time. The statistical performance in the case of additive white Guassian noise is evaluated and an analytical expression for the variance is provided. The simulations using LFM signals with Gaussian envelope testify that IF can be estimated accurately using the peak of WVD for four models of amplitude variation. Furthermore the statistical result of estimation on the signals with amplitude descending before rising is better than that of the signals with constant amplitude when the amplitude variation rate is moderate. 展开更多
关键词 instantaneous frequency linear frequency modulated signals Wigner-Ville distribution statistical performance variance.
下载PDF
Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology 被引量:4
2
作者 姜玉稀 李娇 +2 位作者 冉峰 曹家麟 杨殿雄 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2009年第8期82-89,共8页
Gate-grounded NMOS (GGNMOS) devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS device... Gate-grounded NMOS (GGNMOS) devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS devices are measured using the transmission line pulsing (TLP) measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented. 展开更多
关键词 electrostatic discharge gate-grounded NMOS snapback characteristic layout parameters
原文传递
上一页 1 下一页 到第
使用帮助 返回顶部