The through silicon via(TSV) technology has proven to be the critical enabler to realize a three-dimensional(3D)gigscale system with higher performance but shorter interconnect length. However, the received digital si...The through silicon via(TSV) technology has proven to be the critical enabler to realize a three-dimensional(3D)gigscale system with higher performance but shorter interconnect length. However, the received digital signal after transmission through a TSV channel, composed of redistribution layers(RDLs), TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflection of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient(S11) and signal transmission coefficient(S21) are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance(RLGC)elements of the TSV channel are iterated from scattering(S)-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure(HFSS) simulation software by Ansoft.展开更多
This paper reports that Ni and Ti/4H-SiC Schottky barrier diodes(SBDs) were fabricated and irradiated with 1 MeV electrons up to a dose of 3.43×10^(14) e/cm^2.After radiation,the Schottky barrier heightφb of the...This paper reports that Ni and Ti/4H-SiC Schottky barrier diodes(SBDs) were fabricated and irradiated with 1 MeV electrons up to a dose of 3.43×10^(14) e/cm^2.After radiation,the Schottky barrier heightφb of the Ni/4H-SiC SBD increased from 1.20 eV to 1.21 eV,but decreased from 0.95 eV to 0.94 eV for the Ti/4H-SiC SBD.The degradation ofφB could be explained by interface states of changed Schottky contacts.The on-state resistance R_S of both diodes increased with the dose,which can be ascribed to the radiation defects.The reverse current of the Ni/4H-SiC SBD slightly increased,but for the Ti/4H-SiC SBD it basically remained the same.At room temperature,φB of the diodes recovered completely after one week,and the R_S partly recovered.展开更多
We describe the microfabrication of 85 Rb vapour cells using a glass-silicon anodic bonding technique and in situ chemical reaction between rubidium chloride and barium azide to produce Rb.Under controlled conditions,...We describe the microfabrication of 85 Rb vapour cells using a glass-silicon anodic bonding technique and in situ chemical reaction between rubidium chloride and barium azide to produce Rb.Under controlled conditions,the pure metallic Rb drops and buffer gases were obtained in the cells with a few mm 3 internal volumes during the cell sealing process.At an ambient temperature of 90 C the optical absorption resonance of 85 Rb D1 transition with proper broadening and the corresponding coherent population trapping (CPT) resonance,with a signal contrast of 1.5% and linewidth of about 1.7 kHz,have been detected.The sealing quality and the stability of the cells have also been demonstrated experimentally by using the helium leaking detection and the after-9-month optoelectronics measurement which shows a similar CPT signal as its original status.In addition,the physics package of chip-scale atomic clock (CSAC) based on the cell was realized.The measured frequency stability of the physics package can reach to 2.1×10 10 at one second when the cell was heated to 100 C which proved that the cell has the quality to be used in portable and battery-operated devices.展开更多
Halo structure is added to sub-100 nm surrounding-gate metal-oxide-semiconductor field- effect-transistors (MOS-FETs) to suppress short channel effect. This paper develops the analytical surface potential and threshol...Halo structure is added to sub-100 nm surrounding-gate metal-oxide-semiconductor field- effect-transistors (MOS-FETs) to suppress short channel effect. This paper develops the analytical surface potential and threshold voltage models based on the solution of Poisson's equation in fully depleted condition for symmetric halo-doped cylindrical surrounding gate MOSFETs. The performance of the halo-doped device is studied and the validity of the analytical models is verified by comparing the analytical results with the simulated data by three dimensional numerical device simulator Davinci. It shows that the halo doping profile exhibits better performance in suppressing threshold voltage roll-off and drain-induced barrier lowering, and increasing carrier transport efficiency. The derived analytical models are in good agreement with Davinci.展开更多
To overcome the bulk acoustic wave (BAW), the triple transit signals and the discontinuous frequency band in the first generation surface acoustic wave’s (FGSAW’s) wavelet device, the full transfer multistrip couple...To overcome the bulk acoustic wave (BAW), the triple transit signals and the discontinuous frequency band in the first generation surface acoustic wave’s (FGSAW’s) wavelet device, the full transfer multistrip coupler (MSC) is applied to implement wavelet device, and a novel structure of the second generation surface acoustic wave’s (SGSAW’s) wavelet device is proposed. In the SGSAW’s wavelet device, the BAW is separated and eliminated in different acoustic propagating tracks, and the triple transit signal is suppressed. For arbitrary wavelet scale device, the center frequency is three times the radius of frequency band, which ensures that the frequency band of the SGSAW’s wavelet device is continuous, and avoids losing signals caused by the discontinuation of frequency band. Experimental result confirms that the BAW suppression, ripples in band, receiving loss and insertion loss of the SGSAW’s wavelet device are remarkably improved compared with those of the FGSAW’s wavelet device.展开更多
The effect of high-energy proton irradiation on GaN-based ultraviolet avalanche photodiodes(APDs) is investigated. The dark current of the GaN APD is calculated as a function of the proton energy and proton fluences. ...The effect of high-energy proton irradiation on GaN-based ultraviolet avalanche photodiodes(APDs) is investigated. The dark current of the GaN APD is calculated as a function of the proton energy and proton fluences. By considering the diffusion, generation–recombination, local hopping conductivity, band-to-band tunneling, and trap-assisted tunneling currents, we found that the dark current increases as the proton fluence increases, but decreases with increasing proton energy.展开更多
A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate (DG) MOSFETs from the accumulation to the strong-inversion region.Analytical channel potential relationship is derived f...A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate (DG) MOSFETs from the accumulation to the strong-inversion region.Analytical channel potential relationship is derived from the complete 1-D Poisson equation physically,and the channel potential solution of the DG MOSFET is obtained analytically.The extensive comparisons between the presented solution and the numerical simulation illustrate that the solution is not only accurate and continuous in the whole operation regime of DG MOSFETs,but also valid to wide doping concentration and various geometrical sizes,without employing any fitting parameter.展开更多
Si-PIN photodetectors having features such as low cost,small size,low weight,low voltage,and low power consumption are widely used as radiation detectors in electronic personal dosimeters(EPDs).The technical parameter...Si-PIN photodetectors having features such as low cost,small size,low weight,low voltage,and low power consumption are widely used as radiation detectors in electronic personal dosimeters(EPDs).The technical parameters of EPDs based on the Si-PIN photodetectors include photon energy response(PER),angular response,inherent error,and dose rate linearity.Among them,PER is a key parameter for evaluation of EPD measurement accuracy.At present,owing to the limitations of volume,power consumption,and EPD cost,the PER is usually corrected by a combination of single-channel counting techniques and filtering material methods.However,the above-mentioned methods have problems such as poor PER and low measurement accuracy.To solve such problems,in this study,a 1024-channel spectrometry system using a Si-PIN photodetector was developed and fullspectrum measurement in the reference radiation fields was conducted for radiation protection.The measurement results using the few-channel spectroscopy dose method showed that the PER could be controlled within±14%and±2%under the conditions of two and three energy intervals,respectively,with different channel numbers.The PER measured at 0°angle of radiation incidence meets the-29%to+67%requirements of IEC 61526:2010.Meanwhile,the channel number and counts-to-dose conversion factors formed in the experiment can be integrated into an EPD.展开更多
Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit (3D IC) is predicted exactly. Using the results of this model, a global interconnect design ...Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit (3D IC) is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip (SOC) is established by evaluating the constraints of 1) wiring resource, 2) wiring bandwidth, and 3) wiring noise. In comparison to a two-dimensional integrated circuit (2D IC) in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.展开更多
Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits.Based on the RLC interconnect delay model,by wire sizing,wire spacing and adopting low-swing i...Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits.Based on the RLC interconnect delay model,by wire sizing,wire spacing and adopting low-swing interconnect technology,this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously.The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor(CMOS) interconnect parameters.The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process.The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.展开更多
As the feature size of the CMOS integrated circuit continues to shrink,process variations have become a key factor affecting the interconnect performance.Based on the equivalent Elmore model and the use of the polynom...As the feature size of the CMOS integrated circuit continues to shrink,process variations have become a key factor affecting the interconnect performance.Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method,we propose a linear statistical RCL interconnect delay model,taking into account process variations by successive application of the linear approximation method.Based on a variety of nano-CMOS process parameters,HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%.The proposed model is simple,of high precision,and can be used in the analysis and design of nanometer integrated circuit interconnect systems.展开更多
Based on the multilevel interconnections temperature distribution model and the RLC interconnection delay model of the integrate circuit,this paper proposes a multilevel nano-scale interconnection RLC delay model with...Based on the multilevel interconnections temperature distribution model and the RLC interconnection delay model of the integrate circuit,this paper proposes a multilevel nano-scale interconnection RLC delay model with the method of numerical analysis,the proposed analytical model has summed up the influence of the configuration of multilevel interconnections,the via heat transfer and self-heating effect on the interconnection delay,which is closer to the actual situation.Delay simulation results show that the proposed model has high precision within 5% errors for global interconnections based on the 65 nm CMOS interconnection and material parameter,which can be applied in nanometer CMOS system chip computer-aided design.展开更多
Frank's theory describes that a screw dislocation will produce a pit on the surface,and has been evidenced in many material systems including GaN.However,the size of the pit calculated from the theory deviates sig...Frank's theory describes that a screw dislocation will produce a pit on the surface,and has been evidenced in many material systems including GaN.However,the size of the pit calculated from the theory deviates significantly from experimental result.Through a careful observation of the variations of surface pits and local surface morphology with growing temperature and V/III ratio for c-plane GaN,we believe that Frank's model is valid only in a small local surface area where thermodynamic equilibrium state can be assumed to stay the same.If the kinetic process is too vigorous or too slow to reach a balance,the local equilibrium range will be too small for the center and edge of the screw dislocation spiral to be kept in the same equilibrium state.When the curvature at the center of the dislocation core reaches the critical value 1/r_0,at the edge of the spiral,the accelerating rate of the curvature may not fall to zero,so the pit cannot reach a stationary shape and will keep enlarging under the control of minimization of surface energy to result in a large-sized surface pit.展开更多
On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising cloc...On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.展开更多
By formation of an intermediate semiconductor layer (ISL) with a narrow band gap at the metallic contact/SiC interface, this paper realises a new method to fabricate the low-resistance Ohmic contacts for SiC. An array...By formation of an intermediate semiconductor layer (ISL) with a narrow band gap at the metallic contact/SiC interface, this paper realises a new method to fabricate the low-resistance Ohmic contacts for SiC. An array of transfer length method (TLM) test patterns is formed on N-wells created by P+ ion implantation into Si-faced p-type 4H-SiC epilayer. The ISL of nickel-metal Ohmic contacts to n-type 4H-SiC could be formed by using Germanium ion implantation into SiC. The specific contact resistance ρc as low as 4.23×10-5 Ω·cm2 is achieved after annealing in N2 at 800 ℃ for 3 min, which is much lower than that (> 900℃) in the typical SiC metallisation process. The sheet resistance Rsh of the implanted layers is 1.5 kΩ/□. The technique for converting photoresist into nanocrystalline graphite is used to protect the SiC surface in the annealing after Ge+ ion implantations.展开更多
Stable and persistent bipolar resistive switching was observed in an organic diode with the structure of indium-tin oxide (ITO)/bis(8-hydroxyquinoline) cadmium (Cdq2)/Al. Aggregate formation and electric field driven ...Stable and persistent bipolar resistive switching was observed in an organic diode with the structure of indium-tin oxide (ITO)/bis(8-hydroxyquinoline) cadmium (Cdq2)/Al. Aggregate formation and electric field driven trapping and detrapping of charge carriers in the aggregate states that lie in the energy gap of the highest occupied molecular orbital (HOMO) and the lowest unoccupied molecular orbital (LUMO) of the organic molecule were proposed as the mechanism of the observed bipolar resistive switching, and this was solidly supported by the results of AFM investigations. Repeatedly set, read, and reset measurements demonstrated that the device is potentially applicable in non-volatile memories.展开更多
The magnetoresistance effect of a p–n junction under an electric field which is introduced by the gate voltage at room temperature is investigated by simulation. As auxiliary models, the Lombardi CVT model and carrie...The magnetoresistance effect of a p–n junction under an electric field which is introduced by the gate voltage at room temperature is investigated by simulation. As auxiliary models, the Lombardi CVT model and carrier generationrecombination model are introduced into a drift-diffusion transport model and carrier continuity equations. All the equations are discretized by the finite-difference method and the box integration method and then solved by Newton iteration.Taking advantage of those models and methods, an abrupt junction with uniform doping is studied systematically, and the magnetoresistance as a function of doping concentration, SiO_2 thickness and geometrical size is also investigated. The simulation results show that the magnetoresistance(MR) can be controlled substantially by the gate and is dependent on the polarity of the magnetic field.展开更多
基金Project supported by the National Basic Research Program of China （Grant No 2002CB311904）, the National Defense Basic Research Program of China （Grant No 51327010101） and the National Natural Science Foundation of China （Grant No 60376001）.
基金Project supported by the National Basic Research Program of China （Grant No 2002CB311904）, the National Defense Basic Research Program of China （Grant No 51327010101） and the National Natural Science Foundation of China （Grant No 60376001）.
基金Project supported by the National Natural Science Foundation of China(Grant No.61204044)
文摘The through silicon via(TSV) technology has proven to be the critical enabler to realize a three-dimensional(3D)gigscale system with higher performance but shorter interconnect length. However, the received digital signal after transmission through a TSV channel, composed of redistribution layers(RDLs), TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflection of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient(S11) and signal transmission coefficient(S21) are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance(RLGC)elements of the TSV channel are iterated from scattering(S)-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure(HFSS) simulation software by Ansoft.
基金supported by the National Natural Science Foundation of China(Grant No 60606022)the Xian Applied Materials Foundation of China(Grant No XA-AM-200702)the Advanced Research Foundation of China(Grant No 9140A08050508)
文摘This paper reports that Ni and Ti/4H-SiC Schottky barrier diodes(SBDs) were fabricated and irradiated with 1 MeV electrons up to a dose of 3.43×10^(14) e/cm^2.After radiation,the Schottky barrier heightφb of the Ni/4H-SiC SBD increased from 1.20 eV to 1.21 eV,but decreased from 0.95 eV to 0.94 eV for the Ti/4H-SiC SBD.The degradation ofφB could be explained by interface states of changed Schottky contacts.The on-state resistance R_S of both diodes increased with the dose,which can be ascribed to the radiation defects.The reverse current of the Ni/4H-SiC SBD slightly increased,but for the Ti/4H-SiC SBD it basically remained the same.At room temperature,φB of the diodes recovered completely after one week,and the R_S partly recovered.
基金Project supported by National 863/973 Plans Projects (Grant Nos. 2006AA04Z361,2006CB932402)NSFC (Grant No. 60971002)
文摘We describe the microfabrication of 85 Rb vapour cells using a glass-silicon anodic bonding technique and in situ chemical reaction between rubidium chloride and barium azide to produce Rb.Under controlled conditions,the pure metallic Rb drops and buffer gases were obtained in the cells with a few mm 3 internal volumes during the cell sealing process.At an ambient temperature of 90 C the optical absorption resonance of 85 Rb D1 transition with proper broadening and the corresponding coherent population trapping (CPT) resonance,with a signal contrast of 1.5% and linewidth of about 1.7 kHz,have been detected.The sealing quality and the stability of the cells have also been demonstrated experimentally by using the helium leaking detection and the after-9-month optoelectronics measurement which shows a similar CPT signal as its original status.In addition,the physics package of chip-scale atomic clock (CSAC) based on the cell was realized.The measured frequency stability of the physics package can reach to 2.1×10 10 at one second when the cell was heated to 100 C which proved that the cell has the quality to be used in portable and battery-operated devices.
基金Project supported by the National Natural Science Foundation of China (Grant No 10771168)the State Key Development Program for Basic Research of China (Grant No 2005CB321701)Shaanxi Natural Science Foundation Program of China(Grant No SJ08-ZT13)
文摘Halo structure is added to sub-100 nm surrounding-gate metal-oxide-semiconductor field- effect-transistors (MOS-FETs) to suppress short channel effect. This paper develops the analytical surface potential and threshold voltage models based on the solution of Poisson's equation in fully depleted condition for symmetric halo-doped cylindrical surrounding gate MOSFETs. The performance of the halo-doped device is studied and the validity of the analytical models is verified by comparing the analytical results with the simulated data by three dimensional numerical device simulator Davinci. It shows that the halo doping profile exhibits better performance in suppressing threshold voltage roll-off and drain-induced barrier lowering, and increasing carrier transport efficiency. The derived analytical models are in good agreement with Davinci.
基金This project was supported by the National Natural Science Foundation of China (60476037 ,60176020) and the Doc-toral Foundation of the Ministry of Education of China (20020698014)
文摘To overcome the bulk acoustic wave (BAW), the triple transit signals and the discontinuous frequency band in the first generation surface acoustic wave’s (FGSAW’s) wavelet device, the full transfer multistrip coupler (MSC) is applied to implement wavelet device, and a novel structure of the second generation surface acoustic wave’s (SGSAW’s) wavelet device is proposed. In the SGSAW’s wavelet device, the BAW is separated and eliminated in different acoustic propagating tracks, and the triple transit signal is suppressed. For arbitrary wavelet scale device, the center frequency is three times the radius of frequency band, which ensures that the frequency band of the SGSAW’s wavelet device is continuous, and avoids losing signals caused by the discontinuation of frequency band. Experimental result confirms that the BAW suppression, ripples in band, receiving loss and insertion loss of the SGSAW’s wavelet device are remarkably improved compared with those of the FGSAW’s wavelet device.
基金supported by the National Natural Science Foundation of China(No.61404132)the Fundamental Research Funds for the Central Universities(Nos.lzujbky-2015-302,lzujbky-2017-171,and lzujbky-2016-119)
文摘The effect of high-energy proton irradiation on GaN-based ultraviolet avalanche photodiodes(APDs) is investigated. The dark current of the GaN APD is calculated as a function of the proton energy and proton fluences. By considering the diffusion, generation–recombination, local hopping conductivity, band-to-band tunneling, and trap-assisted tunneling currents, we found that the dark current increases as the proton fluence increases, but decreases with increasing proton energy.
基金Supported by the National Natural Science Foundation of China under Grant Nos 60776024, 60877035 and 90820002, tile National High-Technology Research and Development Program of China under Grant Nos 2007AA03Z427, 2007AA04Z329 and 2007AA04Z254.
基金Project supported by the National Natural Science Foundation of China(Grant No.60876027)the Open Funds of Jiangsu Province Key Lab of ASIC Design(JSICK1007)
文摘A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate (DG) MOSFETs from the accumulation to the strong-inversion region.Analytical channel potential relationship is derived from the complete 1-D Poisson equation physically,and the channel potential solution of the DG MOSFET is obtained analytically.The extensive comparisons between the presented solution and the numerical simulation illustrate that the solution is not only accurate and continuous in the whole operation regime of DG MOSFETs,but also valid to wide doping concentration and various geometrical sizes,without employing any fitting parameter.
基金This work was partly supported by the National Key Scientific Instruments to Develop Dedicated Program(Nos.2013YQ090811 and 2016YFF0103800)the National Key Research and Development Program(No.2017YFF0211100).
文摘Si-PIN photodetectors having features such as low cost,small size,low weight,low voltage,and low power consumption are widely used as radiation detectors in electronic personal dosimeters(EPDs).The technical parameters of EPDs based on the Si-PIN photodetectors include photon energy response(PER),angular response,inherent error,and dose rate linearity.Among them,PER is a key parameter for evaluation of EPD measurement accuracy.At present,owing to the limitations of volume,power consumption,and EPD cost,the PER is usually corrected by a combination of single-channel counting techniques and filtering material methods.However,the above-mentioned methods have problems such as poor PER and low measurement accuracy.To solve such problems,in this study,a 1024-channel spectrometry system using a Si-PIN photodetector was developed and fullspectrum measurement in the reference radiation fields was conducted for radiation protection.The measurement results using the few-channel spectroscopy dose method showed that the PER could be controlled within±14%and±2%under the conditions of two and three energy intervals,respectively,with different channel numbers.The PER measured at 0°angle of radiation incidence meets the-29%to+67%requirements of IEC 61526:2010.Meanwhile,the channel number and counts-to-dose conversion factors formed in the experiment can be integrated into an EPD.
基金supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60676009)the Natural Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2009ZX01034-002-001-005)
文摘Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit (3D IC) is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip (SOC) is established by evaluating the constraints of 1) wiring resource, 2) wiring bandwidth, and 3) wiring noise. In comparison to a two-dimensional integrated circuit (2D IC) in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60971066)the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260)the National Science & Technology Important Project of China (Grant No. 2009ZX01034-002-001-005)
文摘Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits.Based on the RLC interconnect delay model,by wire sizing,wire spacing and adopting low-swing interconnect technology,this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously.The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor(CMOS) interconnect parameters.The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process.The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60725415 and 60971066)the National Science&Technology Important Project of China(Grant No.2009ZX01034-002-001-005)The National Key Laboratory Foundation(Grant No.ZHD200904)
文摘As the feature size of the CMOS integrated circuit continues to shrink,process variations have become a key factor affecting the interconnect performance.Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method,we propose a linear statistical RCL interconnect delay model,taking into account process variations by successive application of the linear approximation method.Based on a variety of nano-CMOS process parameters,HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%.The proposed model is simple,of high precision,and can be used in the analysis and design of nanometer integrated circuit interconnect systems.
基金supported by the National Natural Science Foundation of China (Grant Nos. 60971066 and 60725415)the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260)National Key Laboratory Foundation of China(Grant No. ZHD200904)
文摘Based on the multilevel interconnections temperature distribution model and the RLC interconnection delay model of the integrate circuit,this paper proposes a multilevel nano-scale interconnection RLC delay model with the method of numerical analysis,the proposed analytical model has summed up the influence of the configuration of multilevel interconnections,the via heat transfer and self-heating effect on the interconnection delay,which is closer to the actual situation.Delay simulation results show that the proposed model has high precision within 5% errors for global interconnections based on the 65 nm CMOS interconnection and material parameter,which can be applied in nanometer CMOS system chip computer-aided design.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.11204009 and 61204011)the Beijing Municipal Natural Science Foundation,China(Grant No.4142005)
文摘Frank's theory describes that a screw dislocation will produce a pit on the surface,and has been evidenced in many material systems including GaN.However,the size of the pit calculated from the theory deviates significantly from experimental result.Through a careful observation of the variations of surface pits and local surface morphology with growing temperature and V/III ratio for c-plane GaN,we believe that Frank's model is valid only in a small local surface area where thermodynamic equilibrium state can be assumed to stay the same.If the kinetic process is too vigorous or too slow to reach a balance,the local equilibrium range will be too small for the center and edge of the screw dislocation spiral to be kept in the same equilibrium state.When the curvature at the center of the dislocation core reaches the critical value 1/r_0,at the edge of the spiral,the accelerating rate of the curvature may not fall to zero,so the pit cannot reach a stationary shape and will keep enlarging under the control of minimization of surface energy to result in a large-sized surface pit.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415, 60971066, and 61006028)the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260)the National Key Lab Foundation,China (Grant No. ZHD200904)
文摘On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.
基金Project supported by the National Natural Science Foundation of China (Grant No J54508250120)Xi’an Applied Materials Innovation Fund (Grant No XA-AM-200704)
文摘By formation of an intermediate semiconductor layer (ISL) with a narrow band gap at the metallic contact/SiC interface, this paper realises a new method to fabricate the low-resistance Ohmic contacts for SiC. An array of transfer length method (TLM) test patterns is formed on N-wells created by P+ ion implantation into Si-faced p-type 4H-SiC epilayer. The ISL of nickel-metal Ohmic contacts to n-type 4H-SiC could be formed by using Germanium ion implantation into SiC. The specific contact resistance ρc as low as 4.23×10-5 Ω·cm2 is achieved after annealing in N2 at 800 ℃ for 3 min, which is much lower than that (> 900℃) in the typical SiC metallisation process. The sheet resistance Rsh of the implanted layers is 1.5 kΩ/□. The technique for converting photoresist into nanocrystalline graphite is used to protect the SiC surface in the annealing after Ge+ ion implantations.
基金the National Natural Science Foundation of China(Grant No.10974074)
文摘Stable and persistent bipolar resistive switching was observed in an organic diode with the structure of indium-tin oxide (ITO)/bis(8-hydroxyquinoline) cadmium (Cdq2)/Al. Aggregate formation and electric field driven trapping and detrapping of charge carriers in the aggregate states that lie in the energy gap of the highest occupied molecular orbital (HOMO) and the lowest unoccupied molecular orbital (LUMO) of the organic molecule were proposed as the mechanism of the observed bipolar resistive switching, and this was solidly supported by the results of AFM investigations. Repeatedly set, read, and reset measurements demonstrated that the device is potentially applicable in non-volatile memories.
文摘The magnetoresistance effect of a p–n junction under an electric field which is introduced by the gate voltage at room temperature is investigated by simulation. As auxiliary models, the Lombardi CVT model and carrier generationrecombination model are introduced into a drift-diffusion transport model and carrier continuity equations. All the equations are discretized by the finite-difference method and the box integration method and then solved by Newton iteration.Taking advantage of those models and methods, an abrupt junction with uniform doping is studied systematically, and the magnetoresistance as a function of doping concentration, SiO_2 thickness and geometrical size is also investigated. The simulation results show that the magnetoresistance(MR) can be controlled substantially by the gate and is dependent on the polarity of the magnetic field.
