Photolithography has been a major enabler for the continuous shrink of the semiconductor manufacturing design rules.Throughout the years of the development of the photolithography,many new technologies have been inven...Photolithography has been a major enabler for the continuous shrink of the semiconductor manufacturing design rules.Throughout the years of the development of the photolithography,many new technologies have been invented and successfully implemented,such as image projection lithography,chemically amplified photoresist,phase shifting mask,optical proximity modeling and correction,etc.From 0.25μm technology to the current 7 nm technology,the linewidth has been shrunk from 250 nm to about 20 nm,or 12.5 times.Although imaging resolution is proportional to the illumination wavelength,with the new technologies,the wavelength has only been shrunk from 248 nm to 134.7 nm(193 nm immersion in water),less than 2 times.Would it mean that the imaging performance has been continuously declining?Or we have yet fully utilized the potential of the photolithography technology?In this paper,we will present a study on the key parameters and process window performance of the image projection photolithography from 0.25μm node to the current 7 nm node.展开更多
With the introduction of EUV lithography,the photolithographic process in 5 nm logic process can be simplified to use mostly single exposure method.In a typical 5 nm logic process,the contact-poly pitch(CPP)is 44-50 n...With the introduction of EUV lithography,the photolithographic process in 5 nm logic process can be simplified to use mostly single exposure method.In a typical 5 nm logic process,the contact-poly pitch(CPP)is 44-50 nm,the minimum metal pitch(MPP)is around 30-32 nm.And the overlay budget is estimated to be 2.5 nm(on product overlay).Although the optical resolution of a 0.33NA exposure tool(such as ASML NXE3400)can reach below 32 nm pitch,stochastics in the EUV absorption in photoresists has limited its application to smaller pitches.For the CPP mentioned above,one can use 193 nm immersion lithography with Self-Aligned Double Patterning(SADP)technique to provide good image contrast(or CDU,LWR)as well as good overlay,as for the 10 and 7 nm generations.In the BEOL,however,the 30-32 pitch cannot be realized by a single EUV exposure with enough printing defect process window.If this pitch is to be done by 193 nm immersion lithography,more than 6-8 exposures are needed with very complicated overlay result.For EUV,this can be done through self-aligned LELE with both good CD and overlay control.We have done an optimization of the photolithographic process parameters for the typical metal with a self-developed aerial image simulator based on rigorous coupled wave analysis(RCWA)algorithm and the Abbe imaging routine with an EUV absorption model which describes stochastics.We have calibrated our model with wafer exposure data from several photoresists under collaboration with IMEC.As we have presented last year,to accommodate all pitches under a logic design rule,as well as to provide enough CDU for the logic device performance,in DUV lithography,a typical minimum exposure latitude(EL)for the poly and metal layers can be set at,respectively,18%and 13%.In EUV,due to the existence of stochastics,13%EL,which corresponds to an imaging contrast of 40%,seems not enough for the metal trenches,and to obtain an imaging contrast close to 100%,which yields an EL of 31.4%means that we need to relax minimum pitch to above 41 nm(conventional imaging limit for 0.33NA).This is the best imaging contrast a photolithographic process can provide to reduce LWR and stochastics.In EUV,due to the significantly smaller numerical apertures compared to DUV,the aberration impact can cause much more pronounced image registration error,in order to satisfy 2.5 nm total overlay,the aberration induced shift needs to be kept under 0.2 nm.We have also studied shadowing effect and mask 3D scattering effect and our results will be provided for discussion.展开更多
5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet(EUV)lithography on a large scale.We have done a simulation study for typical 5 nm logic design rule patterns.In a 5 nm...5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet(EUV)lithography on a large scale.We have done a simulation study for typical 5 nm logic design rule patterns.In a 5 nm logic photo process,the most appropriate layers for the EUV lithography are the cut layers,metal layers,and via layers.Generally speaking,critical structures in a lithography process are semi-dense patterns,also known as the“forbidden pitch”patterns,the array edge structures,tip-to-tip structures,tip-to-line structures(under 2D design rules),the minimum area structures,the bi-lines,tri-lines,…,etc.Compared to that from the 193 nm immersion process,the behaviors for the above structures are different.For example,in the 193 nm immersion process,the minimum area is about 2~3 times that of minimum pixel squared,while in EUV photolithographic process,the minimum achievable area is found to be significantly larger.In the simulation,we have kept aware of the stochastics impact due to drastically reduced number of photons absorbed compared to the DUV process,the criteria used for various structures of image contrast are tightened.For example,in 193 nm immersion lithography,we have usually set the minimum Exposure Latitude(EL)for the poly layer,the metal layer,and tip-to-tip pattern,respectively,at 18%,13%,and 10%.However,in EUV lithography,reasonable targets for the minima are,respectively,>18%,18%,and 13%.We have also studied the aberration and shadowing impact to the above design rule structures.We will present the results of our work and our explanations.展开更多
In 5 nm technology node,FinFET device performance is sensitive to the dimension of the device structure such as the fin profile.In this work,we simulate the influence of fin height and fin width to an n-type FinFET.We...In 5 nm technology node,FinFET device performance is sensitive to the dimension of the device structure such as the fin profile.In this work,we simulate the influence of fin height and fin width to an n-type FinFET.We have found that an optimized fin height lies between 50~60 nm.The threshold voltage shift by quantum confinement effect has a steep increase as fin width shrinks to 4 nm.Sharper fin cross section profile gives better subthreshold swing(SS)and stronger drive current because of better gate control.展开更多
文摘Photolithography has been a major enabler for the continuous shrink of the semiconductor manufacturing design rules.Throughout the years of the development of the photolithography,many new technologies have been invented and successfully implemented,such as image projection lithography,chemically amplified photoresist,phase shifting mask,optical proximity modeling and correction,etc.From 0.25μm technology to the current 7 nm technology,the linewidth has been shrunk from 250 nm to about 20 nm,or 12.5 times.Although imaging resolution is proportional to the illumination wavelength,with the new technologies,the wavelength has only been shrunk from 248 nm to 134.7 nm(193 nm immersion in water),less than 2 times.Would it mean that the imaging performance has been continuously declining?Or we have yet fully utilized the potential of the photolithography technology?In this paper,we will present a study on the key parameters and process window performance of the image projection photolithography from 0.25μm node to the current 7 nm node.
文摘With the introduction of EUV lithography,the photolithographic process in 5 nm logic process can be simplified to use mostly single exposure method.In a typical 5 nm logic process,the contact-poly pitch(CPP)is 44-50 nm,the minimum metal pitch(MPP)is around 30-32 nm.And the overlay budget is estimated to be 2.5 nm(on product overlay).Although the optical resolution of a 0.33NA exposure tool(such as ASML NXE3400)can reach below 32 nm pitch,stochastics in the EUV absorption in photoresists has limited its application to smaller pitches.For the CPP mentioned above,one can use 193 nm immersion lithography with Self-Aligned Double Patterning(SADP)technique to provide good image contrast(or CDU,LWR)as well as good overlay,as for the 10 and 7 nm generations.In the BEOL,however,the 30-32 pitch cannot be realized by a single EUV exposure with enough printing defect process window.If this pitch is to be done by 193 nm immersion lithography,more than 6-8 exposures are needed with very complicated overlay result.For EUV,this can be done through self-aligned LELE with both good CD and overlay control.We have done an optimization of the photolithographic process parameters for the typical metal with a self-developed aerial image simulator based on rigorous coupled wave analysis(RCWA)algorithm and the Abbe imaging routine with an EUV absorption model which describes stochastics.We have calibrated our model with wafer exposure data from several photoresists under collaboration with IMEC.As we have presented last year,to accommodate all pitches under a logic design rule,as well as to provide enough CDU for the logic device performance,in DUV lithography,a typical minimum exposure latitude(EL)for the poly and metal layers can be set at,respectively,18%and 13%.In EUV,due to the existence of stochastics,13%EL,which corresponds to an imaging contrast of 40%,seems not enough for the metal trenches,and to obtain an imaging contrast close to 100%,which yields an EL of 31.4%means that we need to relax minimum pitch to above 41 nm(conventional imaging limit for 0.33NA).This is the best imaging contrast a photolithographic process can provide to reduce LWR and stochastics.In EUV,due to the significantly smaller numerical apertures compared to DUV,the aberration impact can cause much more pronounced image registration error,in order to satisfy 2.5 nm total overlay,the aberration induced shift needs to be kept under 0.2 nm.We have also studied shadowing effect and mask 3D scattering effect and our results will be provided for discussion.
文摘5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet(EUV)lithography on a large scale.We have done a simulation study for typical 5 nm logic design rule patterns.In a 5 nm logic photo process,the most appropriate layers for the EUV lithography are the cut layers,metal layers,and via layers.Generally speaking,critical structures in a lithography process are semi-dense patterns,also known as the“forbidden pitch”patterns,the array edge structures,tip-to-tip structures,tip-to-line structures(under 2D design rules),the minimum area structures,the bi-lines,tri-lines,…,etc.Compared to that from the 193 nm immersion process,the behaviors for the above structures are different.For example,in the 193 nm immersion process,the minimum area is about 2~3 times that of minimum pixel squared,while in EUV photolithographic process,the minimum achievable area is found to be significantly larger.In the simulation,we have kept aware of the stochastics impact due to drastically reduced number of photons absorbed compared to the DUV process,the criteria used for various structures of image contrast are tightened.For example,in 193 nm immersion lithography,we have usually set the minimum Exposure Latitude(EL)for the poly layer,the metal layer,and tip-to-tip pattern,respectively,at 18%,13%,and 10%.However,in EUV lithography,reasonable targets for the minima are,respectively,>18%,18%,and 13%.We have also studied the aberration and shadowing impact to the above design rule structures.We will present the results of our work and our explanations.
文摘In 5 nm technology node,FinFET device performance is sensitive to the dimension of the device structure such as the fin profile.In this work,we simulate the influence of fin height and fin width to an n-type FinFET.We have found that an optimized fin height lies between 50~60 nm.The threshold voltage shift by quantum confinement effect has a steep increase as fin width shrinks to 4 nm.Sharper fin cross section profile gives better subthreshold swing(SS)and stronger drive current because of better gate control.
