A multi-deposition multi-annealing technique(MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device's performance. ...A multi-deposition multi-annealing technique(MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device's performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown(TDDB) characteristics of positive channel metal oxide semiconductor(PMOS) under different MDMA process conditions, including the deposition/annealing(D&A) cycles, the D&A time, and the total annealing time. The results show that the increases of the number of D&A cycles(from 1 to 2) and D&A time(from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail(TTF) at 63.2% increases by about several times. However, too many D&A cycles(such as 4 cycles) make the equivalent oxide thickness(EOT) increase by about 1 ?A and the TTF of PMOS worsen. Moreover, different D&A times and numbers of D&A cycles induce different breakdown mechanisms.展开更多
An atmospheric pressure radio-frequency plasma jet that can eject cold plasma has been developed. In this paper, the configuration of this type of plasma jet is illustrated and its discharge characteristics curves are...An atmospheric pressure radio-frequency plasma jet that can eject cold plasma has been developed. In this paper, the configuration of this type of plasma jet is illustrated and its discharge characteristics curves are studied with a current and a voltage probe. A thermal couple is used to measure the temperature distribution along the axis of the jet stream. The temperature distribution curve is generated for the He/O2 jet stream at the discharge power of 150 W. This jet can etch the photo-resistant material at an average rate of 100 nm/min on the surface of silicon wafers at a right angle.展开更多
This study presents a tiny pressure sensor which is used to measure the Intracranial Pressure(ICP). The sensor is based on the piezoresistive effect. The piezoresistive pressure sensor is simulated and designed by usi...This study presents a tiny pressure sensor which is used to measure the Intracranial Pressure(ICP). The sensor is based on the piezoresistive effect. The piezoresistive pressure sensor is simulated and designed by using nonlinear programming optimizing and Finite Element Analysis(FEA) tools. Two kinds of sensor sizes are designed in the case of childhood and adult. The sensors are fabricated by Microelectro Mechanical Systems(MEMS)process. The test results yield sensitivities of 1.033 10 2mV/kPa for the childhood type detection and 1.257 10 2mV/kPa for the adult detection with sensor chip sizes of 0.40 0.40 mm2and 0.50 0.50 mm2,respectively. A novel method for measuring ICP is proposed because of the tiny sizes. Furthermore,relative errors for sensitivity of pressure sensors are limited within 4.76%. Minimum Detectable Pressure(MDP) reaches 128.4 Pa in average.展开更多
In the coexisted world of 3G,4G,5G and many other specialized wireless communication systems,billions of connections could be existing for various information transmission types.Unluckily,data show that the increase o...In the coexisted world of 3G,4G,5G and many other specialized wireless communication systems,billions of connections could be existing for various information transmission types.Unluckily,data show that the increase of network capacity is heavily more than the increase of the network energy efficiency in recent years,which could lead to more energy consumption per transmitted bit in the future network.As basic units in mobile communication systems,microwave/RF components and modules play key roles展开更多
A 40 Gb/s full serializer and deserializer (SerDes) transceiver with controller and physical layer (PHY) is presented.The controller mainly contains protocol transmission, forward error correction and user layer build...A 40 Gb/s full serializer and deserializer (SerDes) transceiver with controller and physical layer (PHY) is presented.The controller mainly contains protocol transmission, forward error correction and user layer build-in self-test (BIST).The physical coding sub-layer (PCS) provides the functions of 64/66 encoder/decoder, PHY BIST, and polarity control.In the physical medium attachment (PMA), both transmitter (TX) and receiver (RX) adopt quarter-rate architecture to relax the timing constraint and reduce power dissipation.The receiver utilizes the phase interpolator (PI) based clock and data recovery (CDR) with bang-bang phase detector (BBPD) to extract the synchronic clock for retiming and de-multiplexing.The multiple-MUX based 4-tap FFE and a two-stage cascade CTLE are employed to mitigate the inter-symbol interference (ISI).In addition, a proposed 4∶1 MUX is used to improve the output jitter performance and reduce the power consumption.Fabricated in a 65 nm CMOS technology, the full transceiver consumes 890 mW at 40 Gb/s and occupies 12 mm 2 .The measurement results show that this transceiver can achieve bit error rate (BER)< 10 -12 after a 15.3 dB loss channel at 20 GHz.展开更多
Chip-on-Film(Co F) is a packaging technology that mounts Integrated Circuits(IC) chips directly on a flexible substrate surface. As both power and the number of pins in such packages increase, thermal conditions becom...Chip-on-Film(Co F) is a packaging technology that mounts Integrated Circuits(IC) chips directly on a flexible substrate surface. As both power and the number of pins in such packages increase, thermal conditions become more important. In this paper, the thermal resistance of Co F packages is studied using Ansys software to perform finite-element analysis. Because of circuit complexity, two equivalent methods—a length-weighted method and an image-recognition method—are proposed in place of an accurate model to get equivalent thermal conductivity of Co F package devices. In our experiments, the simulated value of thermal resistance based on the length-weighted method was 1.653 K/W, and the value based on the image-recognition method was 1.911 K/W. The real thermal resistance value of the Co F package device is 1.812 K/W. So the error between the real value measured by a tester and the simulated value based on the length-weighted method is 8.8%, and the error between the real value and the simulated value based on the image-recognition method is 5.5%. Hence, both methods can provide effective simulation results, and the image-recognition method is more accurate. In addition, we optimized the Co F package structure. From the simulation results, the drop in thermal resistance after the optimization is obvious.展开更多
Graphene-based materials have attracted much attention in recent years. Many researchers have demonstrated prototypes using graphene-based materials, but few specific applications have appeared. Graphenebased acoustic...Graphene-based materials have attracted much attention in recent years. Many researchers have demonstrated prototypes using graphene-based materials, but few specific applications have appeared. Graphenebased acoustic devices have become a popular topic. This paper describes a novel method to fabricate graphenebased earphones by laser scribing. The earphones have been used in wireless communication systems. A wireless communication system was built based on an ARM board. Voice from a mobile phone was transmitted to a graphene-based earphone. The output sound had a similar wave envelope to that of the input; some differences were introduced by the DC bias added to the driving circuit of the graphene-based earphone. The graphene-based earphone was demonstrated to have a great potential in wireless communication.展开更多
AlGaN/GaN high-electron-mobility transistors(HEMTs) with Al-doped ZnO(AZO) transparent gate electrodes are fabricated,and Ni/Au/Ni-gated HEMTs are produced in comparison.The AZO-gated HEMTs show good DC characteristic...AlGaN/GaN high-electron-mobility transistors(HEMTs) with Al-doped ZnO(AZO) transparent gate electrodes are fabricated,and Ni/Au/Ni-gated HEMTs are produced in comparison.The AZO-gated HEMTs show good DC characteristics and Schottky rectifying characteristics,and the gate electrodes achieve excellent transparencies.Compared with Ni/Au/Ni-gated HEMTs,AZO-gated HEMTs show a low saturation current,high threshold voltage,high Schottky barrier height,and low gate reverse leakage current.Due to the higher gate resistivity,AZO-gated HEMTs exhibit a current-gain cutoff frequency(fT) of 10GHz and a power gain cutoff frequency(fmax) of 5GHz,and lower maximum oscillation frequency than Ni/Au/Ni-gated HEMTs.Moreover,the C-V characteristics are measured and the gate interface characteristics of the AZO-gated devices are investigated by a C-V dual sweep.展开更多
In this study,TiN films were deposited on SiO2 substrates by Atomic Layer Deposition(ALD) using TiCl4and NH3 as precursors. Properties and morphology of the TiN films were characterized by different methods.Using Graz...In this study,TiN films were deposited on SiO2 substrates by Atomic Layer Deposition(ALD) using TiCl4and NH3 as precursors. Properties and morphology of the TiN films were characterized by different methods.Using Grazing Incidence X-Ray Diffraction(GIXRD),TiN films demonstrated polycrystalline structure with(111)preferred orientation. Film thickness was measured by Spectroscopic Ellipsometry(SE) and a stable growth rate of 0.0178 nm/cycle was reached after 500 deposition cycles,which was consistent with the essence of ALD as a surface-saturated self-limiting reaction. Film resistivity measured by a four-point probe continuously decreased with increasing deposition cycles until it reached the minimum value of 300μΩ cm at 5000 deposition cycles with a thickness of 87.04 nm. The surface roughness and morphology of the TiN films at different deposition cycles ranging from 50 to 400 were analyzed by Atomic Force Microscopy(AFM). The AFM results indicated that the initial film growth follows the Stranski-Krastanov mode.展开更多
The barrier/seed layer is a key issue in Through Silicon Via(TSV) technology for 3-D integration.Sputtering is an important deposition method for via metallization in semiconductor process. However,due to the limitati...The barrier/seed layer is a key issue in Through Silicon Via(TSV) technology for 3-D integration.Sputtering is an important deposition method for via metallization in semiconductor process. However,due to the limitation of sputtering and a "scallop" profile inside vias,poor step coverage of the barrier/seed layer always occurs in the via metallization process. In this paper,the effects of several sputter parameters(DC power,Ar pressure,deposition time,and substrate temperature) on thin film coverage for TSV applications are investigated.Robust TSVs with aspect ratio 5 1 were obtained with optimized magnetron sputter parameters. In addition,the influences of different sputter parameters are compared and the conclusion could be used as a guideline to select appropriate parameter sets.展开更多
Inspired by real biological neural models,Spiking Neural Networks(SNNs)process information with discrete spikes and show great potential for building low-power neural network systems.This paper proposes a hardware imp...Inspired by real biological neural models,Spiking Neural Networks(SNNs)process information with discrete spikes and show great potential for building low-power neural network systems.This paper proposes a hardware implementation of SNN based on Field-Programmable Gate Arrays(FPGA).It features a hybrid updating algorithm,which combines the advantages of existing algorithms to simplify hardware design and improve performance.The proposed design supports up to 16384 neurons and 16.8 million synapses but requires minimal hardware resources and archieves a very low power consumption of 0.477 W.A test platform is built based on the proposed design using a Xilinx FPGA evaluation board,upon which we deploy a classification task on the MNIST dataset.The evaluation results show an accuracy of 97.06%and a frame rate of 161 frames per second.展开更多
Convolutional Neural Networks(CNNs)are widely used in computer vision,natural language processing,and so on,which generally require low power and high efficiency in real applications.Thus,energy efficiency has become ...Convolutional Neural Networks(CNNs)are widely used in computer vision,natural language processing,and so on,which generally require low power and high efficiency in real applications.Thus,energy efficiency has become a critical indicator of CNN accelerators.Considering that asynchronous circuits have the advantages of low power consumption,high speed,and no clock distribution problems,we design and implement an energy-efficient asynchronous CNN accelerator with a 65 nm Complementary Metal Oxide Semiconductor(CMOS)process.Given the absence of a commercial design tool flow for asynchronous circuits,we develop a novel design flow to implement Click-based asynchronous bundled data circuits efficiently to mask layout with conventional Electronic Design Automation(EDA)tools.We also introduce an adaptive delay matching method and perform accurate static timing analysis for the circuits to ensure correct timing.The accelerator for handwriting recognition network(LeNet-5 model)is implemented.Silicon test results show that the asynchronous accelerator has 30%less power in computing array than the synchronous one and that the energy efficiency of the asynchronous accelerator achieves 1.538 TOPS/W,which is 12%higher than that of the synchronous chip.展开更多
Industrial and agricultural activities lead to the release of rare earth elements(REEs)in wastewater and aquatic ecosystems,and their accumulation in soils.However,the behavior of REEs in soils remains somewhat unclea...Industrial and agricultural activities lead to the release of rare earth elements(REEs)in wastewater and aquatic ecosystems,and their accumulation in soils.However,the behavior of REEs in soils remains somewhat unclear.In the present work the fractionation and fixation of REEs in soddy-podzolic and chernozem soils spiked with La,Ce,and Nd chlorides were studied using dynamic(continuous flow)extraction,which allows natural conditions to be mimicked and artefacts to be minimised.The eluents applied are aimed to dissolve exchangeable,specifically sorbed,bound to Mn oxides,bound to metal-organic complexes,and bound to amorphous and poorly ordered Fe/Al oxides fractions extractable by 0.05 mol/L Ca(NO_(3))2,0.43 mol/L CH_(3)COOH,0.1 mol/L NH_(2)OH·HCl,0.1 mol/L K_(4)P_(2)O_(7) at pH 11,and 0.1 mol/L(NH4)_(2)C_(2)O_(4) at pH 3.2,respectively.It is found that the fixations of added La,Ce,and Nd in the form of metal-organic complexes is predominant for both types of soils:35%-38%in soddy-podzolic soil and 50%-79%in chernozem.The fixation of added elements in the first three fractions(exchangeable,specifically sorbed,and bound to Mn oxides)is significant for soddy-podzolic soil(5%-25%).For chernozem,the relative contents of added Ce and Nd in these fractions are nearly negligible.Only the content of exchangeable La is notable,about 5%.Adding any of three elements(La,Ce,or Nd)at the level of100 mg/kg to an initial sample results in changing the fractionation and bioaccessibility of other REEs present in soil.Their contents increase in the first three fractions and decrease in fifth(oxalate extractable)fraction for both soddy-podzolic soil and chernozem.The main difference is the behavior of REEs in pyrophosphate extractable fraction.For soddy-podzolic soil,adding La,Ce,or Nd results in decreasing the contents of other REEs associated with organic matter.For chernozem,on the contrary,the contents of REEs in the form of metal-organic complexes slightly increase.These processes may be attributed to competitive binding of elements and soil properties;they must be taken into account when assessing the environmental risks of soil pollution with REEs.展开更多
The security of CPU smart cards,which are widely used throughout China,is currently being threatened by side-channel analysis.Typical countermeasures to side-channel analysis involve adding noise and filtering the pow...The security of CPU smart cards,which are widely used throughout China,is currently being threatened by side-channel analysis.Typical countermeasures to side-channel analysis involve adding noise and filtering the power consumption signal.In this paper,we integrate appropriate preprocessing methods with an improved attack strategy to generate a key recovery solution to the shortcomings of these countermeasures.Our proposed attack strategy improves the attack result by combining information leaked from two adjacent clock cycles.Using our laboratory-based power analysis system,we verified the proposed key recovery solution by performing a successful correlation power analysis on a Triple Data Encryption Standard(3DES)hardware module in a real-life 32-bit CPU smart card.All 112 key bits of the 3DES were recovered with about 80 000 power traces.展开更多
Hardware electronic synapse and neuro-inspired computing system based on phase change random access memory(PCRAM)have attracted an extensive investigation.However,due to the intrinsic asymmetric reversible phase trans...Hardware electronic synapse and neuro-inspired computing system based on phase change random access memory(PCRAM)have attracted an extensive investigation.However,due to the intrinsic asymmetric reversible phase transition,the defective weight update of PCRAM synapses in aspects of tuning range,linearity and continuity has long required a system-level complexity of circuits and al-gorithms.The cell-level improvements to a great extent may slim the system thus achieving efficient computing.We report in this work the great enhancement of Ge_(2)Sb_(2)Te_(5)(GST)based PCRAM synapses by combining materials engineering and pulse programming.It is found that carbon doping in GST retards the rate of phase changing thus increasing the controllability of the conductance,while non-linear programmable pulse excitations can eventually lead to a reliable synaptic potentiation and depression.A set of improved programmable pulse schemes for spike-timing dependent plasticity was then demonstrated,suggesting its potential superiority in flexible programming and reliable data collection.Our methods and results are of great significance for implementing PCRAM electronic synapses and high-performance neuro-inspired computing.展开更多
Three main ambipolar compact models for Two-Dimensional(2D)materials based Field-Effect Transistors(2D-FETs)are reviewed:(1)Landauer model,(2)2D Pao-Sah model,and(3)virtual Source Emission-Diffusion(VSED)model.For the...Three main ambipolar compact models for Two-Dimensional(2D)materials based Field-Effect Transistors(2D-FETs)are reviewed:(1)Landauer model,(2)2D Pao-Sah model,and(3)virtual Source Emission-Diffusion(VSED)model.For the Landauer model,the Gauss quadrature method is applied,and it summarizes all kinds of variants,exhibiting its state-of-art.For the 2D Pao-Sah model,the aspects of its theoretical fundamentals are rederived,and the electrostatic potentials of electrons and holes are clarified.A brief development history is compiled for the VSED model.In summary,the Landauer model is naturally appropriate for the ballistic transport of short channels,and the 2D Pao-Sah model is applicable to long-channel devices.By contrast,the VSED model offers a smooth transition between ultimate cases.These three models cover a fairly completed channel length range,which enables researchers to choose the appropriate compact model for their works.展开更多
基金supported by the National High Technology Research and Development Program of China(Grant No.SS2015AA010601)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)
文摘A multi-deposition multi-annealing technique(MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device's performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown(TDDB) characteristics of positive channel metal oxide semiconductor(PMOS) under different MDMA process conditions, including the deposition/annealing(D&A) cycles, the D&A time, and the total annealing time. The results show that the increases of the number of D&A cycles(from 1 to 2) and D&A time(from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail(TTF) at 63.2% increases by about several times. However, too many D&A cycles(such as 4 cycles) make the equivalent oxide thickness(EOT) increase by about 1 ?A and the TTF of PMOS worsen. Moreover, different D&A times and numbers of D&A cycles induce different breakdown mechanisms.
文摘An atmospheric pressure radio-frequency plasma jet that can eject cold plasma has been developed. In this paper, the configuration of this type of plasma jet is illustrated and its discharge characteristics curves are studied with a current and a voltage probe. A thermal couple is used to measure the temperature distribution along the axis of the jet stream. The temperature distribution curve is generated for the He/O2 jet stream at the discharge power of 150 W. This jet can etch the photo-resistant material at an average rate of 100 nm/min on the surface of silicon wafers at a right angle.
基金supported by the National Natural Science Foundation of China (Nos. 61025021 and 61020106006)the National Key Projects of Science and Technology of China (No. 2011ZX02403-002)
文摘This study presents a tiny pressure sensor which is used to measure the Intracranial Pressure(ICP). The sensor is based on the piezoresistive effect. The piezoresistive pressure sensor is simulated and designed by using nonlinear programming optimizing and Finite Element Analysis(FEA) tools. Two kinds of sensor sizes are designed in the case of childhood and adult. The sensors are fabricated by Microelectro Mechanical Systems(MEMS)process. The test results yield sensitivities of 1.033 10 2mV/kPa for the childhood type detection and 1.257 10 2mV/kPa for the adult detection with sensor chip sizes of 0.40 0.40 mm2and 0.50 0.50 mm2,respectively. A novel method for measuring ICP is proposed because of the tiny sizes. Furthermore,relative errors for sensitivity of pressure sensors are limited within 4.76%. Minimum Detectable Pressure(MDP) reaches 128.4 Pa in average.
文摘In the coexisted world of 3G,4G,5G and many other specialized wireless communication systems,billions of connections could be existing for various information transmission types.Unluckily,data show that the increase of network capacity is heavily more than the increase of the network energy efficiency in recent years,which could lead to more energy consumption per transmitted bit in the future network.As basic units in mobile communication systems,microwave/RF components and modules play key roles
基金Sponsored by the National Science Technology Major Project(Grant No.2016ZX01012101)
文摘A 40 Gb/s full serializer and deserializer (SerDes) transceiver with controller and physical layer (PHY) is presented.The controller mainly contains protocol transmission, forward error correction and user layer build-in self-test (BIST).The physical coding sub-layer (PCS) provides the functions of 64/66 encoder/decoder, PHY BIST, and polarity control.In the physical medium attachment (PMA), both transmitter (TX) and receiver (RX) adopt quarter-rate architecture to relax the timing constraint and reduce power dissipation.The receiver utilizes the phase interpolator (PI) based clock and data recovery (CDR) with bang-bang phase detector (BBPD) to extract the synchronic clock for retiming and de-multiplexing.The multiple-MUX based 4-tap FFE and a two-stage cascade CTLE are employed to mitigate the inter-symbol interference (ISI).In addition, a proposed 4∶1 MUX is used to improve the output jitter performance and reduce the power consumption.Fabricated in a 65 nm CMOS technology, the full transceiver consumes 890 mW at 40 Gb/s and occupies 12 mm 2 .The measurement results show that this transceiver can achieve bit error rate (BER)< 10 -12 after a 15.3 dB loss channel at 20 GHz.
基金supported by the National Science and Technology Major Project (No. 2014ZX02503)Wuhan National Laboratory for Optoelectronics (WNLO) for thermal resistance measurement
文摘Chip-on-Film(Co F) is a packaging technology that mounts Integrated Circuits(IC) chips directly on a flexible substrate surface. As both power and the number of pins in such packages increase, thermal conditions become more important. In this paper, the thermal resistance of Co F packages is studied using Ansys software to perform finite-element analysis. Because of circuit complexity, two equivalent methods—a length-weighted method and an image-recognition method—are proposed in place of an accurate model to get equivalent thermal conductivity of Co F package devices. In our experiments, the simulated value of thermal resistance based on the length-weighted method was 1.653 K/W, and the value based on the image-recognition method was 1.911 K/W. The real thermal resistance value of the Co F package device is 1.812 K/W. So the error between the real value measured by a tester and the simulated value based on the length-weighted method is 8.8%, and the error between the real value and the simulated value based on the image-recognition method is 5.5%. Hence, both methods can provide effective simulation results, and the image-recognition method is more accurate. In addition, we optimized the Co F package structure. From the simulation results, the drop in thermal resistance after the optimization is obvious.
基金supported by the National Natural Science Foundation of China (No. 61434001)the National Key Basic Research and Development (973) Program of China (No. 2015CB352100)+1 种基金the National Key Project of Science and Technology (No. 2011ZX02403-002)Special Fund for Agroscientic Research in the Public Interest (201303107) of China
文摘Graphene-based materials have attracted much attention in recent years. Many researchers have demonstrated prototypes using graphene-based materials, but few specific applications have appeared. Graphenebased acoustic devices have become a popular topic. This paper describes a novel method to fabricate graphenebased earphones by laser scribing. The earphones have been used in wireless communication systems. A wireless communication system was built based on an ARM board. Voice from a mobile phone was transmitted to a graphene-based earphone. The output sound had a similar wave envelope to that of the input; some differences were introduced by the DC bias added to the driving circuit of the graphene-based earphone. The graphene-based earphone was demonstrated to have a great potential in wireless communication.
基金supported by the National Key Science & Technology Special Project (Grant No. 2008ZX01002-002)the National Natural Science Foundation of China (Grant No. 61106106)the Fundamental Research Funds for the Central Universities,China (Grant Nos. K50510250003 and K50510250006)
文摘AlGaN/GaN high-electron-mobility transistors(HEMTs) with Al-doped ZnO(AZO) transparent gate electrodes are fabricated,and Ni/Au/Ni-gated HEMTs are produced in comparison.The AZO-gated HEMTs show good DC characteristics and Schottky rectifying characteristics,and the gate electrodes achieve excellent transparencies.Compared with Ni/Au/Ni-gated HEMTs,AZO-gated HEMTs show a low saturation current,high threshold voltage,high Schottky barrier height,and low gate reverse leakage current.Due to the higher gate resistivity,AZO-gated HEMTs exhibit a current-gain cutoff frequency(fT) of 10GHz and a power gain cutoff frequency(fmax) of 5GHz,and lower maximum oscillation frequency than Ni/Au/Ni-gated HEMTs.Moreover,the C-V characteristics are measured and the gate interface characteristics of the AZO-gated devices are investigated by a C-V dual sweep.
基金supported by the National Natural Science Foundation of China (No. 61274111)
文摘In this study,TiN films were deposited on SiO2 substrates by Atomic Layer Deposition(ALD) using TiCl4and NH3 as precursors. Properties and morphology of the TiN films were characterized by different methods.Using Grazing Incidence X-Ray Diffraction(GIXRD),TiN films demonstrated polycrystalline structure with(111)preferred orientation. Film thickness was measured by Spectroscopic Ellipsometry(SE) and a stable growth rate of 0.0178 nm/cycle was reached after 500 deposition cycles,which was consistent with the essence of ALD as a surface-saturated self-limiting reaction. Film resistivity measured by a four-point probe continuously decreased with increasing deposition cycles until it reached the minimum value of 300μΩ cm at 5000 deposition cycles with a thickness of 87.04 nm. The surface roughness and morphology of the TiN films at different deposition cycles ranging from 50 to 400 were analyzed by Atomic Force Microscopy(AFM). The AFM results indicated that the initial film growth follows the Stranski-Krastanov mode.
基金supported by the National Natural Science Foundation of China (No. 61274111)he National Science & Technology Major Project of China (No. 2011ZX02709)
文摘The barrier/seed layer is a key issue in Through Silicon Via(TSV) technology for 3-D integration.Sputtering is an important deposition method for via metallization in semiconductor process. However,due to the limitation of sputtering and a "scallop" profile inside vias,poor step coverage of the barrier/seed layer always occurs in the via metallization process. In this paper,the effects of several sputter parameters(DC power,Ar pressure,deposition time,and substrate temperature) on thin film coverage for TSV applications are investigated.Robust TSVs with aspect ratio 5 1 were obtained with optimized magnetron sputter parameters. In addition,the influences of different sputter parameters are compared and the conclusion could be used as a guideline to select appropriate parameter sets.
基金supported in part by the Beijing Innovation Center for Future Chip,Tsinghua Universityin part by the Science and Technology Innovation Special Zone project,Chinain part by the Tsinghua University Initiative Scientific Research Program(No.2018Z05JDX005).
文摘Inspired by real biological neural models,Spiking Neural Networks(SNNs)process information with discrete spikes and show great potential for building low-power neural network systems.This paper proposes a hardware implementation of SNN based on Field-Programmable Gate Arrays(FPGA).It features a hybrid updating algorithm,which combines the advantages of existing algorithms to simplify hardware design and improve performance.The proposed design supports up to 16384 neurons and 16.8 million synapses but requires minimal hardware resources and archieves a very low power consumption of 0.477 W.A test platform is built based on the proposed design using a Xilinx FPGA evaluation board,upon which we deploy a classification task on the MNIST dataset.The evaluation results show an accuracy of 97.06%and a frame rate of 161 frames per second.
基金supported by National Science and Technology Major Project from Minister of Science and Technology,China(No.2018AAA0103100)the National Natural Science Foundation of China(No.61674090)+1 种基金partly supported by Beijing National Research Center for Information Science and Technology(No.042003266)Beijing Engineering Research Center(No.BG0149)。
文摘Convolutional Neural Networks(CNNs)are widely used in computer vision,natural language processing,and so on,which generally require low power and high efficiency in real applications.Thus,energy efficiency has become a critical indicator of CNN accelerators.Considering that asynchronous circuits have the advantages of low power consumption,high speed,and no clock distribution problems,we design and implement an energy-efficient asynchronous CNN accelerator with a 65 nm Complementary Metal Oxide Semiconductor(CMOS)process.Given the absence of a commercial design tool flow for asynchronous circuits,we develop a novel design flow to implement Click-based asynchronous bundled data circuits efficiently to mask layout with conventional Electronic Design Automation(EDA)tools.We also introduce an adaptive delay matching method and perform accurate static timing analysis for the circuits to ensure correct timing.The accelerator for handwriting recognition network(LeNet-5 model)is implemented.Silicon test results show that the asynchronous accelerator has 30%less power in computing array than the synchronous one and that the energy efficiency of the asynchronous accelerator achieves 1.538 TOPS/W,which is 12%higher than that of the synchronous chip.
基金Project supported by the Russian Science Foundation(16-13-10417)the Russian Foundation for Basic Research(19-05-50016)+1 种基金Ministry of Science and Higher Education of the Russian Federation(K1-2014-026,K2-2020-003)Vernadsky Institute of Geochemistry and Analytical Chemistry,Russian Academy of Sciences(0116-2019-0010)。
文摘Industrial and agricultural activities lead to the release of rare earth elements(REEs)in wastewater and aquatic ecosystems,and their accumulation in soils.However,the behavior of REEs in soils remains somewhat unclear.In the present work the fractionation and fixation of REEs in soddy-podzolic and chernozem soils spiked with La,Ce,and Nd chlorides were studied using dynamic(continuous flow)extraction,which allows natural conditions to be mimicked and artefacts to be minimised.The eluents applied are aimed to dissolve exchangeable,specifically sorbed,bound to Mn oxides,bound to metal-organic complexes,and bound to amorphous and poorly ordered Fe/Al oxides fractions extractable by 0.05 mol/L Ca(NO_(3))2,0.43 mol/L CH_(3)COOH,0.1 mol/L NH_(2)OH·HCl,0.1 mol/L K_(4)P_(2)O_(7) at pH 11,and 0.1 mol/L(NH4)_(2)C_(2)O_(4) at pH 3.2,respectively.It is found that the fixations of added La,Ce,and Nd in the form of metal-organic complexes is predominant for both types of soils:35%-38%in soddy-podzolic soil and 50%-79%in chernozem.The fixation of added elements in the first three fractions(exchangeable,specifically sorbed,and bound to Mn oxides)is significant for soddy-podzolic soil(5%-25%).For chernozem,the relative contents of added Ce and Nd in these fractions are nearly negligible.Only the content of exchangeable La is notable,about 5%.Adding any of three elements(La,Ce,or Nd)at the level of100 mg/kg to an initial sample results in changing the fractionation and bioaccessibility of other REEs present in soil.Their contents increase in the first three fractions and decrease in fifth(oxalate extractable)fraction for both soddy-podzolic soil and chernozem.The main difference is the behavior of REEs in pyrophosphate extractable fraction.For soddy-podzolic soil,adding La,Ce,or Nd results in decreasing the contents of other REEs associated with organic matter.For chernozem,on the contrary,the contents of REEs in the form of metal-organic complexes slightly increase.These processes may be attributed to competitive binding of elements and soil properties;they must be taken into account when assessing the environmental risks of soil pollution with REEs.
基金supported by the Major Program“Core of Electronic DevicesHigh-End General Chips+1 种基金and Basis of Software Products”of the Ministry of Industry and Information Technology of China(No.2014ZX01032205)the Key Technologies Research and Development Program of the Twelfth Five-Year Plan of China(No.MMJJ201401009)
文摘The security of CPU smart cards,which are widely used throughout China,is currently being threatened by side-channel analysis.Typical countermeasures to side-channel analysis involve adding noise and filtering the power consumption signal.In this paper,we integrate appropriate preprocessing methods with an improved attack strategy to generate a key recovery solution to the shortcomings of these countermeasures.Our proposed attack strategy improves the attack result by combining information leaked from two adjacent clock cycles.Using our laboratory-based power analysis system,we verified the proposed key recovery solution by performing a successful correlation power analysis on a Triple Data Encryption Standard(3DES)hardware module in a real-life 32-bit CPU smart card.All 112 key bits of the 3DES were recovered with about 80 000 power traces.
基金This work was supported by Key R&D Program of Shaanxi Province of China(2020GY-271 and 2018ZDXM-GY-150)the Fundamental Research Funds for the Central Universities(xjj2018016)+3 种基金the“111 Project”of China(B14040),the Open Project of State Key Laboratory of Electronic Thin Films and Integrated Devices(KFJJ201902)the Open Project of State Key Laboratory of Information Functional Materials(SKL-201908)the Natural Sci-ences and Engineering Research Council of Canada(NSERC,Dis-covery Grant No.RGPIN-2017-06915)the National Natural Science Foundation of China(91964204 and 61634008).
文摘Hardware electronic synapse and neuro-inspired computing system based on phase change random access memory(PCRAM)have attracted an extensive investigation.However,due to the intrinsic asymmetric reversible phase transition,the defective weight update of PCRAM synapses in aspects of tuning range,linearity and continuity has long required a system-level complexity of circuits and al-gorithms.The cell-level improvements to a great extent may slim the system thus achieving efficient computing.We report in this work the great enhancement of Ge_(2)Sb_(2)Te_(5)(GST)based PCRAM synapses by combining materials engineering and pulse programming.It is found that carbon doping in GST retards the rate of phase changing thus increasing the controllability of the conductance,while non-linear programmable pulse excitations can eventually lead to a reliable synaptic potentiation and depression.A set of improved programmable pulse schemes for spike-timing dependent plasticity was then demonstrated,suggesting its potential superiority in flexible programming and reliable data collection.Our methods and results are of great significance for implementing PCRAM electronic synapses and high-performance neuro-inspired computing.
基金supported by the National Key R&D Program(Nos.2016YFA0200400 and 2018YFC2001202)the National Natural Science Foundation of China(Nos.61434001,61574083,61874065,51861145202,and U20A20168)+3 种基金the support of the Research Fund from Tsinghua University Initiative Scientific Research ProgramBeijing Innovation Center for Future ChipBeijing Natural Science Foundation(No.4184091)Tsinghua-Fuzhou Institute for Date Technology(No.TFIDT2018008)。
文摘Three main ambipolar compact models for Two-Dimensional(2D)materials based Field-Effect Transistors(2D-FETs)are reviewed:(1)Landauer model,(2)2D Pao-Sah model,and(3)virtual Source Emission-Diffusion(VSED)model.For the Landauer model,the Gauss quadrature method is applied,and it summarizes all kinds of variants,exhibiting its state-of-art.For the 2D Pao-Sah model,the aspects of its theoretical fundamentals are rederived,and the electrostatic potentials of electrons and holes are clarified.A brief development history is compiled for the VSED model.In summary,the Landauer model is naturally appropriate for the ballistic transport of short channels,and the 2D Pao-Sah model is applicable to long-channel devices.By contrast,the VSED model offers a smooth transition between ultimate cases.These three models cover a fairly completed channel length range,which enables researchers to choose the appropriate compact model for their works.
