On the basis of thermodynamic and kinetic consideration of Ge-O system,high-pressure oxidation(HPO)on Ge was proposed to suppress the GeO desorption during the thermal oxidation and significant improvements of Ge/GeO2...On the basis of thermodynamic and kinetic consideration of Ge-O system,high-pressure oxidation(HPO)on Ge was proposed to suppress the GeO desorption during the thermal oxidation and significant improvements of Ge/GeO2-based gate stacks have been achieved.It is found that the post oxidation annealing at lower temperatures is helpful to passivate the interface defects at the Ge/GeO2 stack generated by the conventional thermal oxidation,while the high-quality GeO2 bulk properties can only be achieved by HPO that grows GeO2 film at high temperatures without the GeO desorption.This paper reviews the advantage of HPO on the formation of Ge/GeO2 stacks in terms of Ge/GeO2 interface and GeO2 bulk properties.展开更多
Editorial Introduction: China's IC industry has been flourishing in recent years, huge market demand together with government investments are the major driving forces for this development. The status and developme...Editorial Introduction: China's IC industry has been flourishing in recent years, huge market demand together with government investments are the major driving forces for this development. The status and development momentum of the Chinese IC industry also attracted wide interest and attention of international counterparts. A group of domestic IC experts are invited by the JoMM to write a series of articles about China's IC industry, including the history, current status, development, and related government policies. Information in these articles is all from public data from recent years. The purpose of these articles is to enhance mutual understanding between the Chinese domestic IC industry and international IC ecosystem. The following article is the third one of this series, the status quo of China's IC industry. The IC industry chain is very long including design, manufacturing, special equipment, materials, packaging and testing. The article series are arranged in accordance with this scope.展开更多
1.Introduction In recent years,China's semiconductor equipment industry has made considerable progress,some key equipment have been developed,achieving a revolutionary breakthrough.Meanwhile,a great number of dome...1.Introduction In recent years,China's semiconductor equipment industry has made considerable progress,some key equipment have been developed,achieving a revolutionary breakthrough.Meanwhile,a great number of domestic equipment have been applied to large mass production lines,indicating new progress in industrialization.From the policy perspective,the state has continuously introduced policies to support the localization of the semiconductor industry,and has invested more than 100 billion yuan to boost the development of the semiconductor industry chain since 2014.展开更多
This paper summarizes the status of the plasma etch process modeling research.It mainly introduces typical etching models employing the analytical method,geometric method,system identification method,basic principle s...This paper summarizes the status of the plasma etch process modeling research.It mainly introduces typical etching models employing the analytical method,geometric method,system identification method,basic principle simulation method,as well as empirical model.Each model’s basic principles,application scopes,advantages and disadvantages are discussed.Based on these,the development history of the etch process modeling is summarized,and the development opportunities of the etch model are prospected.This paper provides a brief view for establishment of the plasma etching process model.展开更多
A reflective faceted structure is proposed to reshaping an incoherent light beam into two focalized spots-To obtain the desired irradiance distribution on a detector,custom optimization function is written,and the two...A reflective faceted structure is proposed to reshaping an incoherent light beam into two focalized spots-To obtain the desired irradiance distribution on a detector,custom optimization function is written,and the two dimensional tilt angles of each facet are optimized automatically in a pure non-sequential mode in Zemax OpticStudio 16.The result is also confirmed inside LightTools&2 from Synopsys.For measuring the quality of the optimization result in the case of two spots focalization,four factors including efficiency on the detector,uniformity,the root mean square error and the correlation coefficient are calculated.These four factors are used to evaluate the influence of several parameters on the irradiance distribution.These parameters include the incidence angle,the divergence angle,the facet size,the source type and the resolution of the facet angular positions.Finally,an analysis of those parameters is made and the performance of this type of component is demonstrated.展开更多
Scanning electron microscope(SEM)metrology is critical in semiconductor manufacturing for patterning process quality assessment and monitoring.Besides feature width and feature-feature space dimension measurements fro...Scanning electron microscope(SEM)metrology is critical in semiconductor manufacturing for patterning process quality assessment and monitoring.Besides feature width and feature-feature space dimension measurements from critical dimension SEM(CDSEM)images,visual inspection of SEM image also offers rich information on the quality of patterning.However,visual inspection alone leaves considerable room of ambiguity regarding patterning quality.To narrow the room of ambiguity and to obtain more statistically quantitative information on patterning quality,SEM-image contours are often extracted to serve such purposes.From contours,important information such as critical dimension and resist sidewall angle at any location can be estimated.Those geometrical information can be used for optical proximity correction(OPC)model verification and lithography hotspot detection,etc.Classical contour extraction algorithms based on local information have insufficient capability in dealing with noisy and low contrast images.To achieve reliable contours from noisy and low contrast images,information beyond local should be made use of as much as possible.In this regard,deep convolutional neural network(DCNN)has proven its great capability,as manifested in various computer vision tasks.Taking the full advantages of this maturing technology,we have designed a DCNN network and applied it to the task of extracting contours from noisy and low contrast SEM images.It turns out that the model is capable of separating the resist top and bottom contours reliably.In addition,the model does not generate false contours,it also can suppress the generation of broken contours when ambiguous area for contour extraction is small and non-detrimental.With advanced image alignment algorithm with sub-pixel accuracy,contours from different exposure fields of same process condition can be superposed to estimate process variation band,furthermore,stochastic effect induced edge placement variation statistics can easily be inferred from the extracted contours.展开更多
5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet(EUV)lithography on a large scale.We have done a simulation study for typical 5 nm logic design rule patterns.In a 5 nm...5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet(EUV)lithography on a large scale.We have done a simulation study for typical 5 nm logic design rule patterns.In a 5 nm logic photo process,the most appropriate layers for the EUV lithography are the cut layers,metal layers,and via layers.Generally speaking,critical structures in a lithography process are semi-dense patterns,also known as the“forbidden pitch”patterns,the array edge structures,tip-to-tip structures,tip-to-line structures(under 2D design rules),the minimum area structures,the bi-lines,tri-lines,…,etc.Compared to that from the 193 nm immersion process,the behaviors for the above structures are different.For example,in the 193 nm immersion process,the minimum area is about 2~3 times that of minimum pixel squared,while in EUV photolithographic process,the minimum achievable area is found to be significantly larger.In the simulation,we have kept aware of the stochastics impact due to drastically reduced number of photons absorbed compared to the DUV process,the criteria used for various structures of image contrast are tightened.For example,in 193 nm immersion lithography,we have usually set the minimum Exposure Latitude(EL)for the poly layer,the metal layer,and tip-to-tip pattern,respectively,at 18%,13%,and 10%.However,in EUV lithography,reasonable targets for the minima are,respectively,>18%,18%,and 13%.We have also studied the aberration and shadowing impact to the above design rule structures.We will present the results of our work and our explanations.展开更多
Photolithography has been a major enabler for the continuous shrink of the semiconductor manufacturing design rules.Throughout the years of the development of the photolithography,many new technologies have been inven...Photolithography has been a major enabler for the continuous shrink of the semiconductor manufacturing design rules.Throughout the years of the development of the photolithography,many new technologies have been invented and successfully implemented,such as image projection lithography,chemically amplified photoresist,phase shifting mask,optical proximity modeling and correction,etc.From 0.25μm technology to the current 7 nm technology,the linewidth has been shrunk from 250 nm to about 20 nm,or 12.5 times.Although imaging resolution is proportional to the illumination wavelength,with the new technologies,the wavelength has only been shrunk from 248 nm to 134.7 nm(193 nm immersion in water),less than 2 times.Would it mean that the imaging performance has been continuously declining?Or we have yet fully utilized the potential of the photolithography technology?In this paper,we will present a study on the key parameters and process window performance of the image projection photolithography from 0.25μm node to the current 7 nm node.展开更多
An i-Line chemically amplified(ICA)thick film positive resist is reported in this paper.The impact of process conditions on photoresist performance was investigated.Pre-apply bake temperature and post exposure bake te...An i-Line chemically amplified(ICA)thick film positive resist is reported in this paper.The impact of process conditions on photoresist performance was investigated.Pre-apply bake temperature and post exposure bake temperature affect acid diffusion and deblocking reactions,thus playing an integral role in defining the resist profile.Both pre-apply bake delay and post exposure delay(PED)affect critical dimension(CD)variation,but PED is more sensitive to contact with airborne contaminants.Different polymers and different photo-acid generators(PAG)are also illustrated in this work.By optimizing the structure and concentration of key components,an ICA resist with good environment stability and excellent lithographic performance was demonstrated.展开更多
Yield control in the integrated circuit manufacturing process is very important,and defects are one of the main factors affecting chip yield.As the process control becomes more and more critical and the critical dimen...Yield control in the integrated circuit manufacturing process is very important,and defects are one of the main factors affecting chip yield.As the process control becomes more and more critical and the critical dimension becomes smaller and smaller,the identification and location of defects is particularly important.This paper uses a machine learning algorithm based on transfer learning and two fine-tuned neural network models to realize the autonomous recognition and classification of defects even the data set is small,which achieves 94.6%and 91.7%classification accuracy.The influence of network complexity on classification result is studied at the same time.This paper also establishes a visual display algorithm of defects,shows the process of extracting the deep-level features of the defective image by the network,and then analyze the defect features.Finally,the Gradient-weighted Class Activation Mapping technology is used to generate defect heat maps,which locate the defect positions and probability intensity effects.This paper greatly expands the application of transfer learning in the field of integrated circuit lithography defect recognition,and greatly improves the friendliness of defect display.展开更多
Editorial Introduction:China's IC industry has been flourishing in recent years,huge market demand together with government investments are the major driving forces for this development.The status and development ...Editorial Introduction:China's IC industry has been flourishing in recent years,huge market demand together with government investments are the major driving forces for this development.The status and development momentum of the Chinese IC industry also attracted wide interest and attention of international counterparts.A group of domestic IC experts are invited by the JoMM to write a series of articles about China's IC industry,including the history,current status,development,and related government policies.Information in these articles is all from public data from recent years.The purpose of these articles is to enhance mutual understanding between the Chinese domestic IC industry and international IC ecosystem.展开更多
With the continuous scaling in conventional CMOS technologies,the planar MOSFET device is limited by the severe short-channel-effect(SCE),Multi-gate FETs(MuG-FET)such as FinFETs and Nanowire,Nanosheet devices have eme...With the continuous scaling in conventional CMOS technologies,the planar MOSFET device is limited by the severe short-channel-effect(SCE),Multi-gate FETs(MuG-FET)such as FinFETs and Nanowire,Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22 nm node.The multi-gate structure has better short channel behaviors due to enhanced control from the multiple gates.Due to the relatively more mature process and rich learning of the device physics,the FinFET is still extended to 5 nm technology node.In this paper,we proposed a 5 nm FINFET device,which is based on typical 5 nm logic design rules.To achieve the challenging device performance target,which is around 15%speed gain or 25%power reduction against the 7 nm device,we have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability.Based on our preferred device architecture,we provide our brief process flow,key dimensions,and simulated device DC/AC performance,like Vt,Idsat,SS,DIBL and parasitic parameters.As a part of the final evaluation,RO simulation result has been checked,which demonstrates that the Performance Per Area(PPA)is close to industry reference 5 nm performance.展开更多
Technology roadmaps have been a part of the semiconductor industry for many years.The first roadmap was Moore’s law,which started as an empirical observation that competitive forces then turned into a prediction that...Technology roadmaps have been a part of the semiconductor industry for many years.The first roadmap was Moore’s law,which started as an empirical observation that competitive forces then turned into a prediction that became an industry roadmap.Then the ITRS roadmap was developed and for many years was used by leading edge semiconductor producers to drive new technology they needed.Now there is the IRDS roadmap,which projects semiconductor end user requirements and develops a technology roadmap based on those requirements.The 2017 IRDS roadmap was just released.To prepare the roadmap,we received input from experts around the world.The roadmap predicts that the requirements of high performance logic will drive the development of different device structures in logic chips.Memory technology will also advance but is more focused on cost than high performance logic is.Because of this,there may be a split in the patterning roadmaps for different types of devices.Logic will adopt EUV and its extensions,while flash memory will consider nanoimprint.Directed self-assembly and direct write e-beam are also being developed.DSA has the potential to improve CD uniformity and lower costs.Direct write e-beam promises to make personalization of chips more feasible.DRAM memory will trail logic in critical dimensions and will adopt EUV when it becomes cost effective.The lithography community will both have to make EUV work and overcome the challenges of randomness in CDs and resist performance,while memory will try to make nanoimprint a reliable and low defect method of patterning.Long term,logic is expected to start focusing on 3D architectures in the late 2020’s.This will put a tremendous stress on the yield of patterning processes and on reducing the number of process steps that are required.It will also put more focus on hole type patterns,which will become one of the key patterning challenges in the future.展开更多
Micro-sieves have been widely used in medical treatment,quarantine,environment,agriculture,pharmacy and food processing.However,the manufacturing and yield improvement have been difficult due to multiple challenges,su...Micro-sieves have been widely used in medical treatment,quarantine,environment,agriculture,pharmacy and food processing.However,the manufacturing and yield improvement have been difficult due to multiple challenges,such as the sieve unit release defect,cracking,and KOH corrosion.In this paper,we report process details and discuss technical difficulties which are usually the root-causes for process failures,and demonstrate a reliable and high yield production of SiNx micro-sieves processed with our novel method,which is also compatible with high volume manufacturing.展开更多
This paper presents the latest status of the open source advanced TCAD simulator called Nano-Electronic Simulation Software(NESS)which is currently under development at the Device Modeling Group of the University of G...This paper presents the latest status of the open source advanced TCAD simulator called Nano-Electronic Simulation Software(NESS)which is currently under development at the Device Modeling Group of the University of Glasgow.NESS is designed with the main aim to provide an open,flexible,and easy to use simulation environment where users are able not only to perform numerical simulations but also to develop and implement new simulation methods and models.Currently,NESS is organized into two main components:the structure generator and a collection of different numerical solvers;which are linked to supporting components such as an effective mass extractor and materials database.This paper gives a brief overview of each of the components by describing their main capabilities,structure,and theory behind each one of them.Moreover,to illustrate the capabilities of each component,here we have given examples considering various device structures,architectures,materials,etc.at multiple simulation conditions.We expect that NESS will prove to be a great tool for both conventional as well as exploratory device research programs and projects.展开更多
Editorial Introduction:China's IC industry has been flourishing in recent years,huge market demand together with government investments are the major driving forces for this development.The status and development ...Editorial Introduction:China's IC industry has been flourishing in recent years,huge market demand together with government investments are the major driving forces for this development.The status and development momentum of the Chinese IC industry also attracted wide interest and attention of international counterparts.A group of domestic IC experts are invited by the JoMM to write a series of articles about China's IC industry,including the history,current status,development,and related government policies.Information in these articles is all from public data from recent years.The purpose of these articles is to enhance mutual understanding between the Chinese domestic IC industry and international IC ecosystem.展开更多
3D NAND technical development and manufacturing face many challenges to scale down their devices,and metrology stands out as much more difficult at each turn.Unlike planar NAND,3D NAND has a three-dimensional vertical...3D NAND technical development and manufacturing face many challenges to scale down their devices,and metrology stands out as much more difficult at each turn.Unlike planar NAND,3D NAND has a three-dimensional vertical structure with high-aspect ratio.Obviously top-down images is not enough for process control,instead inner structure control becomes much more important than before,e.g.channel hole profiles.Besides,multi-layers,special materials and YMTC unique X-Tacking technology also bring other metrology challenges:high wafer bow,stress induced overlay,opaque film measurement.Technical development can adopt some destructive methodology(TEM,etch-back SEM),while manufacturing can only use nondestructive method.These drive some new metrology development,including X-Ray,mass measure and Mid-IR spectroscopy.As 3D NAND suppliers move to>150 layers devices,the existing metrology tools will be pushed to the limits.Still,the metrology must innovate.展开更多
In 1964 Hermann Gummel published the first numerical solution method for the onedimensional Drift Diffusion model.In his seminal paper[1]already the nonlinear iteration method and the basics of the discretization meth...In 1964 Hermann Gummel published the first numerical solution method for the onedimensional Drift Diffusion model.In his seminal paper[1]already the nonlinear iteration method and the basics of the discretization method named after him are outlined.Soon after this paper appeared many research groups worldwide tried to solve the Drift Diffusion equations in two and more dimensions applying predominantly general finite element discretization methods which were very popular at these days.Due to this a large variety of different codes solving the multidimensional Drift Diffusion equations based on many different space discretization schemes existed in the seventies.However already in the nineties all Drift Diffusion simulators being of importance for semiconductor device design in industry and academia still used Gummel’s nonlinear iteration method but were entirely based on just one specialized space discretization method,which incorporates the basic ideas of the Scharfetter-Gummel discretization scheme[2].All other codes which were not based on this special space discretization method had nearly vanished already in the nineties and this is still the case today.This paper tries to shed some light on the hidden reasons for this astonishing development.展开更多
Editorial Introduction:China's IC industry has been flourishing in recent years,huge market demand together with government investments are the major driving forces for this development.The status and development ...Editorial Introduction:China's IC industry has been flourishing in recent years,huge market demand together with government investments are the major driving forces for this development.The status and development momentum of the Chinese IC industry also attracted wide interest and attention of international counterparts.A group of domestic IC experts are invited by the JoMM to write a series of articles about China's IC industry,including the history,current status,development,and related government policies.Information in these articles is all from public data from recent years.The purpose of these articles is to enhance mutual understanding between the Chinese domestic IC industry and international IC ecosystem.展开更多
3D NAND(three-dimensional NAND type)has rapidly become the standard technology for enterprise flash memories,and is also gaining widespread use in other applications.Continued manufacturing process improvements are es...3D NAND(three-dimensional NAND type)has rapidly become the standard technology for enterprise flash memories,and is also gaining widespread use in other applications.Continued manufacturing process improvements are essential in delivering memory devices with higher I/O performance,higher bit density,and at lower cost.Current 3D NAND technology involves process steps that form array and peripheral CMOS(Complementary Metal-Oxide-Semiconductor)regions side-by-side,resulting in waste of silicon real estate and film stress compromises,and limits the paths of making advanced 3D NAND devices.An innovative architecture was invented to overcome these challenges by connecting two wafers electrically through metal VIAs(Vertical Interconnect Access)[1].Highly accurate and efficient metrology is required to monitor VIA interface due to increased process complexity and precision requirements.With the advanced processing of AFM(Atomic Force Microscopy)images,highly accurate and precise measurements have been achieved.An inline pattern-centric metrology solution that is designed for high volume mass production of high-performance 3D NAND is presented in this paper.展开更多
基金The author would like to thank Prof.Akira Toriumi,Prof.Kita Koji,Prof.Kosuke Nagashio,and Dr.Tomonori Nishimura at the University of Tokyo for their continuous support and encouragement,which induced the main results reviewed in this paper.
文摘On the basis of thermodynamic and kinetic consideration of Ge-O system,high-pressure oxidation(HPO)on Ge was proposed to suppress the GeO desorption during the thermal oxidation and significant improvements of Ge/GeO2-based gate stacks have been achieved.It is found that the post oxidation annealing at lower temperatures is helpful to passivate the interface defects at the Ge/GeO2 stack generated by the conventional thermal oxidation,while the high-quality GeO2 bulk properties can only be achieved by HPO that grows GeO2 film at high temperatures without the GeO desorption.This paper reviews the advantage of HPO on the formation of Ge/GeO2 stacks in terms of Ge/GeO2 interface and GeO2 bulk properties.
文摘Editorial Introduction: China's IC industry has been flourishing in recent years, huge market demand together with government investments are the major driving forces for this development. The status and development momentum of the Chinese IC industry also attracted wide interest and attention of international counterparts. A group of domestic IC experts are invited by the JoMM to write a series of articles about China's IC industry, including the history, current status, development, and related government policies. Information in these articles is all from public data from recent years. The purpose of these articles is to enhance mutual understanding between the Chinese domestic IC industry and international IC ecosystem. The following article is the third one of this series, the status quo of China's IC industry. The IC industry chain is very long including design, manufacturing, special equipment, materials, packaging and testing. The article series are arranged in accordance with this scope.
文摘1.Introduction In recent years,China's semiconductor equipment industry has made considerable progress,some key equipment have been developed,achieving a revolutionary breakthrough.Meanwhile,a great number of domestic equipment have been applied to large mass production lines,indicating new progress in industrialization.From the policy perspective,the state has continuously introduced policies to support the localization of the semiconductor industry,and has invested more than 100 billion yuan to boost the development of the semiconductor industry chain since 2014.
文摘This paper summarizes the status of the plasma etch process modeling research.It mainly introduces typical etching models employing the analytical method,geometric method,system identification method,basic principle simulation method,as well as empirical model.Each model’s basic principles,application scopes,advantages and disadvantages are discussed.Based on these,the development history of the etch process modeling is summarized,and the development opportunities of the etch model are prospected.This paper provides a brief view for establishment of the plasma etching process model.
基金supported by Natural Science Foundation of Shandong Province,China(No.ZR2019BF033).
文摘A reflective faceted structure is proposed to reshaping an incoherent light beam into two focalized spots-To obtain the desired irradiance distribution on a detector,custom optimization function is written,and the two dimensional tilt angles of each facet are optimized automatically in a pure non-sequential mode in Zemax OpticStudio 16.The result is also confirmed inside LightTools&2 from Synopsys.For measuring the quality of the optimization result in the case of two spots focalization,four factors including efficiency on the detector,uniformity,the root mean square error and the correlation coefficient are calculated.These four factors are used to evaluate the influence of several parameters on the irradiance distribution.These parameters include the incidence angle,the divergence angle,the facet size,the source type and the resolution of the facet angular positions.Finally,an analysis of those parameters is made and the performance of this type of component is demonstrated.
文摘Scanning electron microscope(SEM)metrology is critical in semiconductor manufacturing for patterning process quality assessment and monitoring.Besides feature width and feature-feature space dimension measurements from critical dimension SEM(CDSEM)images,visual inspection of SEM image also offers rich information on the quality of patterning.However,visual inspection alone leaves considerable room of ambiguity regarding patterning quality.To narrow the room of ambiguity and to obtain more statistically quantitative information on patterning quality,SEM-image contours are often extracted to serve such purposes.From contours,important information such as critical dimension and resist sidewall angle at any location can be estimated.Those geometrical information can be used for optical proximity correction(OPC)model verification and lithography hotspot detection,etc.Classical contour extraction algorithms based on local information have insufficient capability in dealing with noisy and low contrast images.To achieve reliable contours from noisy and low contrast images,information beyond local should be made use of as much as possible.In this regard,deep convolutional neural network(DCNN)has proven its great capability,as manifested in various computer vision tasks.Taking the full advantages of this maturing technology,we have designed a DCNN network and applied it to the task of extracting contours from noisy and low contrast SEM images.It turns out that the model is capable of separating the resist top and bottom contours reliably.In addition,the model does not generate false contours,it also can suppress the generation of broken contours when ambiguous area for contour extraction is small and non-detrimental.With advanced image alignment algorithm with sub-pixel accuracy,contours from different exposure fields of same process condition can be superposed to estimate process variation band,furthermore,stochastic effect induced edge placement variation statistics can easily be inferred from the extracted contours.
文摘5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet(EUV)lithography on a large scale.We have done a simulation study for typical 5 nm logic design rule patterns.In a 5 nm logic photo process,the most appropriate layers for the EUV lithography are the cut layers,metal layers,and via layers.Generally speaking,critical structures in a lithography process are semi-dense patterns,also known as the“forbidden pitch”patterns,the array edge structures,tip-to-tip structures,tip-to-line structures(under 2D design rules),the minimum area structures,the bi-lines,tri-lines,…,etc.Compared to that from the 193 nm immersion process,the behaviors for the above structures are different.For example,in the 193 nm immersion process,the minimum area is about 2~3 times that of minimum pixel squared,while in EUV photolithographic process,the minimum achievable area is found to be significantly larger.In the simulation,we have kept aware of the stochastics impact due to drastically reduced number of photons absorbed compared to the DUV process,the criteria used for various structures of image contrast are tightened.For example,in 193 nm immersion lithography,we have usually set the minimum Exposure Latitude(EL)for the poly layer,the metal layer,and tip-to-tip pattern,respectively,at 18%,13%,and 10%.However,in EUV lithography,reasonable targets for the minima are,respectively,>18%,18%,and 13%.We have also studied the aberration and shadowing impact to the above design rule structures.We will present the results of our work and our explanations.
文摘Photolithography has been a major enabler for the continuous shrink of the semiconductor manufacturing design rules.Throughout the years of the development of the photolithography,many new technologies have been invented and successfully implemented,such as image projection lithography,chemically amplified photoresist,phase shifting mask,optical proximity modeling and correction,etc.From 0.25μm technology to the current 7 nm technology,the linewidth has been shrunk from 250 nm to about 20 nm,or 12.5 times.Although imaging resolution is proportional to the illumination wavelength,with the new technologies,the wavelength has only been shrunk from 248 nm to 134.7 nm(193 nm immersion in water),less than 2 times.Would it mean that the imaging performance has been continuously declining?Or we have yet fully utilized the potential of the photolithography technology?In this paper,we will present a study on the key parameters and process window performance of the image projection photolithography from 0.25μm node to the current 7 nm node.
文摘An i-Line chemically amplified(ICA)thick film positive resist is reported in this paper.The impact of process conditions on photoresist performance was investigated.Pre-apply bake temperature and post exposure bake temperature affect acid diffusion and deblocking reactions,thus playing an integral role in defining the resist profile.Both pre-apply bake delay and post exposure delay(PED)affect critical dimension(CD)variation,but PED is more sensitive to contact with airborne contaminants.Different polymers and different photo-acid generators(PAG)are also illustrated in this work.By optimizing the structure and concentration of key components,an ICA resist with good environment stability and excellent lithographic performance was demonstrated.
基金Thanks for the support of the National Natural Science Foundation of China(61604172,61874002)and the Key Laboratory of Microelectronic Devices and Integration Technology.The authors would like to thank Y.B.Feng from YMTC for the helpful discussions.
文摘Yield control in the integrated circuit manufacturing process is very important,and defects are one of the main factors affecting chip yield.As the process control becomes more and more critical and the critical dimension becomes smaller and smaller,the identification and location of defects is particularly important.This paper uses a machine learning algorithm based on transfer learning and two fine-tuned neural network models to realize the autonomous recognition and classification of defects even the data set is small,which achieves 94.6%and 91.7%classification accuracy.The influence of network complexity on classification result is studied at the same time.This paper also establishes a visual display algorithm of defects,shows the process of extracting the deep-level features of the defective image by the network,and then analyze the defect features.Finally,the Gradient-weighted Class Activation Mapping technology is used to generate defect heat maps,which locate the defect positions and probability intensity effects.This paper greatly expands the application of transfer learning in the field of integrated circuit lithography defect recognition,and greatly improves the friendliness of defect display.
文摘Editorial Introduction:China's IC industry has been flourishing in recent years,huge market demand together with government investments are the major driving forces for this development.The status and development momentum of the Chinese IC industry also attracted wide interest and attention of international counterparts.A group of domestic IC experts are invited by the JoMM to write a series of articles about China's IC industry,including the history,current status,development,and related government policies.Information in these articles is all from public data from recent years.The purpose of these articles is to enhance mutual understanding between the Chinese domestic IC industry and international IC ecosystem.
基金The authors would like to thank the management team and all our team members in Shanghai ICRD center.
文摘With the continuous scaling in conventional CMOS technologies,the planar MOSFET device is limited by the severe short-channel-effect(SCE),Multi-gate FETs(MuG-FET)such as FinFETs and Nanowire,Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22 nm node.The multi-gate structure has better short channel behaviors due to enhanced control from the multiple gates.Due to the relatively more mature process and rich learning of the device physics,the FinFET is still extended to 5 nm technology node.In this paper,we proposed a 5 nm FINFET device,which is based on typical 5 nm logic design rules.To achieve the challenging device performance target,which is around 15%speed gain or 25%power reduction against the 7 nm device,we have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability.Based on our preferred device architecture,we provide our brief process flow,key dimensions,and simulated device DC/AC performance,like Vt,Idsat,SS,DIBL and parasitic parameters.As a part of the final evaluation,RO simulation result has been checked,which demonstrates that the Performance Per Area(PPA)is close to industry reference 5 nm performance.
文摘Technology roadmaps have been a part of the semiconductor industry for many years.The first roadmap was Moore’s law,which started as an empirical observation that competitive forces then turned into a prediction that became an industry roadmap.Then the ITRS roadmap was developed and for many years was used by leading edge semiconductor producers to drive new technology they needed.Now there is the IRDS roadmap,which projects semiconductor end user requirements and develops a technology roadmap based on those requirements.The 2017 IRDS roadmap was just released.To prepare the roadmap,we received input from experts around the world.The roadmap predicts that the requirements of high performance logic will drive the development of different device structures in logic chips.Memory technology will also advance but is more focused on cost than high performance logic is.Because of this,there may be a split in the patterning roadmaps for different types of devices.Logic will adopt EUV and its extensions,while flash memory will consider nanoimprint.Directed self-assembly and direct write e-beam are also being developed.DSA has the potential to improve CD uniformity and lower costs.Direct write e-beam promises to make personalization of chips more feasible.DRAM memory will trail logic in critical dimensions and will adopt EUV when it becomes cost effective.The lithography community will both have to make EUV work and overcome the challenges of randomness in CDs and resist performance,while memory will try to make nanoimprint a reliable and low defect method of patterning.Long term,logic is expected to start focusing on 3D architectures in the late 2020’s.This will put a tremendous stress on the yield of patterning processes and on reducing the number of process steps that are required.It will also put more focus on hole type patterns,which will become one of the key patterning challenges in the future.
文摘Micro-sieves have been widely used in medical treatment,quarantine,environment,agriculture,pharmacy and food processing.However,the manufacturing and yield improvement have been difficult due to multiple challenges,such as the sieve unit release defect,cracking,and KOH corrosion.In this paper,we report process details and discuss technical difficulties which are usually the root-causes for process failures,and demonstrate a reliable and high yield production of SiNx micro-sieves processed with our novel method,which is also compatible with high volume manufacturing.
基金the European Union Horizon 2020 research and innovation programme under grant agreement No.688101 SUPERAID7 and has received further funding from EPSRC UKRI Innovation Fellowship scheme under grant agreement No.EP/S001131/1(QSEE),No.EP/P009972/1(QUANTDEVMOD)and No.EP/S000259/1(Variability PDK for design based research on FPGA/neuro computing)and from H2020-FETOPEN-2019 scheme under grant agreement No.862539-Electromed-FET OPEN.
文摘This paper presents the latest status of the open source advanced TCAD simulator called Nano-Electronic Simulation Software(NESS)which is currently under development at the Device Modeling Group of the University of Glasgow.NESS is designed with the main aim to provide an open,flexible,and easy to use simulation environment where users are able not only to perform numerical simulations but also to develop and implement new simulation methods and models.Currently,NESS is organized into two main components:the structure generator and a collection of different numerical solvers;which are linked to supporting components such as an effective mass extractor and materials database.This paper gives a brief overview of each of the components by describing their main capabilities,structure,and theory behind each one of them.Moreover,to illustrate the capabilities of each component,here we have given examples considering various device structures,architectures,materials,etc.at multiple simulation conditions.We expect that NESS will prove to be a great tool for both conventional as well as exploratory device research programs and projects.
文摘Editorial Introduction:China's IC industry has been flourishing in recent years,huge market demand together with government investments are the major driving forces for this development.The status and development momentum of the Chinese IC industry also attracted wide interest and attention of international counterparts.A group of domestic IC experts are invited by the JoMM to write a series of articles about China's IC industry,including the history,current status,development,and related government policies.Information in these articles is all from public data from recent years.The purpose of these articles is to enhance mutual understanding between the Chinese domestic IC industry and international IC ecosystem.
基金The authors would like to thank all YMTC metrology vendors for helping with tool evaluation,data collection and data analysis.
文摘3D NAND technical development and manufacturing face many challenges to scale down their devices,and metrology stands out as much more difficult at each turn.Unlike planar NAND,3D NAND has a three-dimensional vertical structure with high-aspect ratio.Obviously top-down images is not enough for process control,instead inner structure control becomes much more important than before,e.g.channel hole profiles.Besides,multi-layers,special materials and YMTC unique X-Tacking technology also bring other metrology challenges:high wafer bow,stress induced overlay,opaque film measurement.Technical development can adopt some destructive methodology(TEM,etch-back SEM),while manufacturing can only use nondestructive method.These drive some new metrology development,including X-Ray,mass measure and Mid-IR spectroscopy.As 3D NAND suppliers move to>150 layers devices,the existing metrology tools will be pushed to the limits.Still,the metrology must innovate.
文摘In 1964 Hermann Gummel published the first numerical solution method for the onedimensional Drift Diffusion model.In his seminal paper[1]already the nonlinear iteration method and the basics of the discretization method named after him are outlined.Soon after this paper appeared many research groups worldwide tried to solve the Drift Diffusion equations in two and more dimensions applying predominantly general finite element discretization methods which were very popular at these days.Due to this a large variety of different codes solving the multidimensional Drift Diffusion equations based on many different space discretization schemes existed in the seventies.However already in the nineties all Drift Diffusion simulators being of importance for semiconductor device design in industry and academia still used Gummel’s nonlinear iteration method but were entirely based on just one specialized space discretization method,which incorporates the basic ideas of the Scharfetter-Gummel discretization scheme[2].All other codes which were not based on this special space discretization method had nearly vanished already in the nineties and this is still the case today.This paper tries to shed some light on the hidden reasons for this astonishing development.
文摘Editorial Introduction:China's IC industry has been flourishing in recent years,huge market demand together with government investments are the major driving forces for this development.The status and development momentum of the Chinese IC industry also attracted wide interest and attention of international counterparts.A group of domestic IC experts are invited by the JoMM to write a series of articles about China's IC industry,including the history,current status,development,and related government policies.Information in these articles is all from public data from recent years.The purpose of these articles is to enhance mutual understanding between the Chinese domestic IC industry and international IC ecosystem.
文摘3D NAND(three-dimensional NAND type)has rapidly become the standard technology for enterprise flash memories,and is also gaining widespread use in other applications.Continued manufacturing process improvements are essential in delivering memory devices with higher I/O performance,higher bit density,and at lower cost.Current 3D NAND technology involves process steps that form array and peripheral CMOS(Complementary Metal-Oxide-Semiconductor)regions side-by-side,resulting in waste of silicon real estate and film stress compromises,and limits the paths of making advanced 3D NAND devices.An innovative architecture was invented to overcome these challenges by connecting two wafers electrically through metal VIAs(Vertical Interconnect Access)[1].Highly accurate and efficient metrology is required to monitor VIA interface due to increased process complexity and precision requirements.With the advanced processing of AFM(Atomic Force Microscopy)images,highly accurate and precise measurements have been achieved.An inline pattern-centric metrology solution that is designed for high volume mass production of high-performance 3D NAND is presented in this paper.
